Flashback to Basics Friday! Bifurcation...
Pop quiz! Which section of the PCI Express Base Specification covers bifurcation? Here, I’ll even wait while you look….
Did you give up yet? Good. First of all, you won’t find the word “bifurcation” in the spec at all! The term is commonly understood to mean splitting a set of PCI Express lanes into multiple links – and it’s most common on Root Complexes. So for example, our friendly neighborhood Root Complex (RC) vendor builds an RC with 16 lanes – but he knows that in some uses the RC will connect to a single x16 link, while in others his customers only want x4 links. Rather than waste the 12 now unused lanes, wouldn’t it be nice to instead be able to configure those 16 total lanes as 4 links each of x4 width?
To read the full article, click here
Related Semiconductor IP
- PCI Express Verification IP
- Scalable Switch Intel® FPGA IP for PCI Express
- Configurable PCI Express 4.0 Link Controller
- PCI Express Gen 1/2/3/4 Phy
- PCI Express Gen 1/2/3/4 Phy
Related Blogs
- Flashback to Basics Friday! Bandwidth...
- Black Friday and the Predicted Semiconductor Shortages
- Basics of Functional Verification
- Functional Verification Basics: What's The Objective of End of Test?
Latest Blogs
- Automated, Faster Specification to Sign-Off with IDS-AI
- NovaTech Automation Crius PIU: Bringing Conventional Instrument Transformers onto the IEC 61850 Process Bus
- Single Pair Ethernet and TSN: The In-Robot Network Behind the Next Humanoid Robots
- A design path to success exists for ultra-low-voltage SoCs
- Where Routine Flow Ends Veriest Formal Expertise Begins