New details on Altera network-on-FPGA
August 29, 2014
Advantages to using NoCs in SoC design are well documented: reduced routing congestion, better performance than crossbars, improved optimization and reuse of IP, strategies for system power management, and so on. What happens when NoCs move into FPGAs, or more accurately the SoC variant combining ARM cores with programmable logic?
To read the full article, click here
Related Semiconductor IP
- DDR5/DDR4 and LPDDR5/LPDDR4 EMIF FPGA IP
- JESD204 FPGA IP
- 25G Ethernet Intel® FPGA IP
- Nios® V Processor
- RLDRAM II Controller Intel® FPGA IP
Related Blogs
- PLD Overview: Xilinx and Altera
- Xilinx ARMs FPGAs, Altera to MIPSify Them
- Is Altera Looking At Programmable DSP?
- Altera purchases optical network IP vendor Avalon Microelectronics
Latest Blogs
- Building the engine behind Arm’s silicon shift
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects