UMC's Integrated DFM Solutions Target Today's 90nm SoC Designers
DFM capabilities, including quick yield ramping service, readily available
HSINCHU, Taiwan, March 1, 2006-UMC (NYSE: UMC, TSE: 2303), a leading global semiconductor company, today announced its comprehensive design-for-manufacturing (DFM), yield optimization offering targeted to customers developing 90nm SoCs. The package incorporates DFM elements into standard-cell libraries, SPICE models and design flows to provide users with yield-enhancing knowledge throughout the design and manufacturing stages.
UMC's DFM Value Service, a key part of the DFM package, includes a comprehensive design for diagnostic platform that enables UMC to test, map out and pinpoint physical failures on customers' chips quickly, without the extensive and drawn-out process of exchanging information back and forth between the foundry and customer. Through this approach, engineering teams spend less effort on the diagnostic process and thus they can quickly enhance yields, gain faster time to market, and have lower production costs.
Lee Chung, vice president of corporate marketing at UMC, said, "With the rising complexity of 90nm and below designs, meeting time to market objectives has become increasingly difficult for today's SoC designers. UMC's manufacturing teams collaborated closely with our customers' design teams to achieve the common goal of quick ramp up to high and stable yields for SoC designs. This means customers can get their SoC designs from the development stage to market quickly and with greater cost efficiencies."
UMC's DFM package incorporates the following elements:
DFM Counselor-the comprehensive documents and models for guiding users throughout the design phase. It features a Design Support Manual covering:
- DFM recommended rules, guidelines and Optical Proximity Correction (OPC) guidelines
- SPICE models including Length of Diffusion (LOD) effects and Monte Carlo models
- Intercap models including Wire Edge Effects (WEE)
- DFM Application Note
DFM Counselor Tools-the comprehensive software programs and technology files supporting all major EDA tools for implementing the DFM features:
- DFM scripts for double-VIA insertion and limiting VIA stacking
- DFM DRC decks for checking the recommended DFM rules
- DFM Layout Parameter Extraction (LPE) and Layout vs. Schematic (LVS) technology files for supporting the inclusion of WEE and LOD effects
DFM Value Service-the DFM services completed at UMC in order to give customers the best value:
- Post tapeout OPC and Lithography Rule Check (LRC)
- Metal dummy fill
- Metal slotting
- UMC's proprietary Design for Diagnostics yield ramping service created so that customers' engineering teams can minimize their time required on the diagnostic process
DFM Premium Service-the optional DFM service provided by UMC to those customers desiring to check their OPC/LRC results prior to tapeout
Customers seeking to utilize UMC's integrated DFM solutions should contact their account manager or go to the MyUMC total online supply chain customer information portal at www.umc.com.
About UMC
UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced process ICs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge foundry technologies that enable sophisticated system-on-chip (SoC) designs, including volume production 90nm, industry-leading 65nm, and mixed signal/RFCMOS. UMC's 10 wafer manufacturing facilities include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 12,000 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com.
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related News
- UMC Brings Comprehensive Reference Design Flow to 90nm SoC Designers
- Siemens collaborates with UMC to develop 3D integrated circuit hybrid-bonding workflow
- Mobiveil's PSRAM Controller IP Lets SoC Designers Leverage AP Memory's Xccela x8/x16 250 MHz PSRAM Memory
- Movellus Announces Industry-First Integrated Droop Response System for SoCs
Latest News
- How hardware-assisted verification (HAV) transforms EDA workflows
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology