TVS releases one of the first C-PHY VIP solutions in the market
March 3, 2015 -- TVS releases one of the first C-PHY UVM VIP which has extensive constrained random stimuli generation capabilities, configurable monitors and checks to ensure protocol compliance to MIPI standard for C-PHY specification 1.0.
Pre-defined coverage bins enable easier extension and coverage collection. The VIP has been verified for protocol compliance with asureSign-TVS’ in-house Requirements tracking tool.
For information, please visit here or contact us at sales@testandverification.com
Related Semiconductor IP
- HBM4 PHY IP
- eFuse Controller IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related News
- Arasan announces the immediate availability of its MIPI C-PHY / D-PHY Combo IP for SoC Designs on TSMC 22nm Process
- Arasan announces its next generation of C-PHY/ D-PHY Combo IP Core compliant with the latest MIPI Specifications
- Arasan announces MIPI DSI IP for FPGA supporting full C-PHY 2.0 speeds
- Arasan announces MIPI CSI IP for FPGA supporting full C-PHY 2.0 speeds
Latest News
- LTSCT and Andes Technology Sign Strategic IP Licensing Master Agreement to accelerate RISC-V Based Advanced Semiconductor Solutions
- Global Semiconductor Sales Increase 29.8% Year-to-Year in November
- BAE Systems Licenses Time Sensitive Networking (TSN) Ethernet IP Cores from CAST
- HBM4 Mass Production Delayed to End of 1Q26 By Spec Upgrades and Nvidia Strategy Adjustments
- ASICLAND Secures USD 17.6 Million Storage Controller Mass Production Contract