Synopsys Announces Next-Generation VC SpyGlass RTL Static Signoff Platform

Delivers 3X Higher Performance, Multi-Billion Gate Capacity, and 10X Lower Noise

MOUNTAIN VIEW, Calif., Feb. 27, 2020 -- Synopsys, Inc. (Nasdaq: SNPS), today announced general availability of the VC SpyGlass^™ RTL Static Signoff platform, part of the Synopsys Verification Continuum^™ platform, which builds on the proven SpyGlass^® technology. The VC SpyGlass platform with multi-core support increases performance by 3X with half the memory footprint. The next-generation platform is enhanced with machine learning technology to reduce noise by 10X with no loss in quality of results using trusted industry-standard SpyGlass engines.

"The noise reduction technology in VC SpyGlass enabled us to focus on debugging real issues and discover clock domain crossing issues previously not found," said Duen-Min Wang, SoC Engineering Director at SK Hynix. "In addition, the consistent design behavior between VC SpyGlass and Synopsys Design Compiler reduced our design setup to a single day, with more flexible debug and custom constraints settings."

Increasing SoC complexity demands verifying correct construction of RTL, clock domain crossing (CDC), and reset domain crossing (RDC) early in the RTL phase of development. Synopsys VC SpyGlass integrates advanced algorithms and analysis techniques that provides designers detailed information and insights about their design much earlier in the RTL phase. It provides a tightly integrated solution for formal-enabled linting to reduce noise and comprehensive CDC and RDC analysis to catch logic issues added during implementation. VC SpyGlass is also natively integrated with Synopsys' Verdi^® automated debug system to accelerate root cause analysis for bugs. In addition, the VC SpyGlass platform uses design behavior and Tcl flow consistent with Synopsys' Design Compiler^® and PrimeTime^® tools to significantly reduce setup time between implementation and verification flows.

"Insufficient or incorrect constraints are the primary reason for a large number of violations, which increases our debug cycles," said Hideyuki Okabe, director of the Digital Design Technology Department, Shared R&D Division, IoT and Infrastructure Business Unit at Renesas Electronics Corporation. "The new machine learning technology in VC SpyGlass will help our design teams to significantly reduce the number of false CDC violations to debug, enabling much faster identification of root cause."

"A tightly integrated RTL static verification platform is essential for customers to accelerate time to market and reduce iterations," said Rajiv Maheshwary, VP of marketing and business development in the Verification Group at Synopsys. "VC SpyGlass delivers 3X higher performance, multi-billion gate capacity, and 10X less noise. Coupled with tight integration of Lint, CDC and RDC analysis, and compatibility with the implementation flow, SoC teams are able to increase overall productivity and accelerate RTL static signoff."

Availability and Resources

The Synopsys VC SpyGlass RTL static signoff platform is available now. Current SpyGlass users can easily upgrade to VC SpyGlass, using existing rules and scripts.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software^™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.