sci-worx demonstrates its fitness for the IP boom Unique range: qualified and certified IP modules
sci-worx demonstrates its fitness for the IP boom Unique range: qualified and certified IP modules
Munich/Hanover, 21 November 2000 - sci-worx is presenting its extended range of qualified and certified intellectual property (IP) modules at the electronica 2000 trade fair.
The Hanover-based company is markedly expanding its activities in the area of qualification and certification for its IP modules, marketed as DesignObjects® (DO). In order to guarantee unified quality for all its modules, sci-worx has revised its complete range. Based on the VSIA deliverables specifications for delivery goods, sci-worx has defined a two-stage process consisting of a formal and a physical qualification. sci-worx has set up the "IP publishing" department for this qualification process which acts more or less as an in-house customer.
Investigations are carried out in the following areas for the formal qualification:
· completness checks,
· code analysis,
· code coverage,
· low power analysis,
· synthesis analysis,
· timing verification,
· scan insertion,
· test pattern generation,
· test coverage.
Doing physical qualification, the DO is verified in an exemplary close-to-realistic environment with the help of an FPGA. The result of the qualification is an extensive certificate which is also a component of supply.
According to a study carried out by the Dataquest market research company, the IP market is one of the most rapidly expanding segments in the semiconductor industry. sci-worx, with its DesignObjects®, is now placed at Rank 9 within the worldwide IP providers and occupies fifth place in Europe (Dataquest May 2000).
Related Semiconductor IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- LLM AI IP Core
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
Related News
- CAST Expands Functional Safety Line with Additional Certified IP Cores
- Qualitas Semiconductor Successfully Demonstrates Live UCIe PHY IP at AI Infra Summit 2025
- Creonic Updates Doppler Channel IP Core with Extended Frequency Band and Sampling Range
- Is the world ready for Platypus, Zero ASIC’s open eFPGA IP? CEO Andreas Olofsson is betting that the answer is “Yes”
Latest News
- RISC-V Exceeding Expectations in AI, China Deployment
- BrainChip and Parsons Sign Strategic Agreement to Accelerate Edge AI Defense Systems
- Ainekko Brings Open-Source Principles to AI Hardware with Launch of AI Foundry
- Arteris Selected by Axelera AI to Accelerate Computer Vision for Edge Devices
- Preliminary Characterisation Report for Perceptia’s pPLL08W in GF 22FDX Now Available