OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium
MILPITAS, Calif. -- Jun 16, 2022 -- OpenFive, a leading provider of custom silicon solutions with differentiated IP, today announced that the company has joined the Universal Chiplet Interconnect Express (UCIe) Consortium as it continues to contribute to open industry standards and ecosystems that accelerate deployment of chiplet connectivity solutions. These solutions deliver power efficient, high-throughput, and low-latency connectivity for High Performance Computing (HPC), datacenter, and cloud applications.
OpenFive will actively participate in the Electrical and Protocol subgroups. OpenFive will leverage its depth of experience from multiple customer engagements and its silicon platforms. These include OpenFive Die-to-Die (D2D) Controller and PHY IP on leading-edge silicon process nodes down to 5nm combined with advanced 2.5D packaging.
OpenFive has played an instrumental role in supporting various chiplet interconnects based on Open High Bandwidth Interface (OHBI) and (Bunch-of-Wire) BoW, through the Open Domain Specific Architecture (ODSA) chapter under the Open Compute Project (OCP). OpenFive introduced the industry’s first Die-to-Die (D2D) Controllers which are agnostic to physical link interfaces and has been awarded multiple customer design wins.
“The addition of UCIe support to our existing OHBI and BoW D2D products is a natural progression for OpenFive, and will allow our customers to choose from a complete D2D product portfolio optimized for HPC and Networking chiplets,” said Ketan Mehta, Senior Director of Interface Products Marketing at OpenFive. “By combining our D2D IP with our custom silicon implementation capabilities, and 2.5D advanced package design experience, OpenFive is well positioned to deliver a complete end-to-end chiplet solution.”
About OpenFive
OpenFive, a SiFive business unit, is focused on custom silicon solutions and differentiated IP. With spec-to-silicon design capabilities, customizable SoC platforms, and differentiated IP for Artificial Intelligence, Cloud/Datacenter, High Performance Computing, Networking, and Storage applications, OpenFive is uniquely positioned to deliver highly competitive processor agnostic domain-specific SoCs.
The OpenFive IP portfolio includes High-Bandwidth Memory (HBM3/2E) and low power LPDDR5/4x memory subsystems; Die-to-Die (D2D) interface IP subsystems for heterogeneous multi-die connectivity including chiplets; low-latency, high-throughput Interlaken interface IP for chip-to-chip connectivity; 400/800G Ethernet MAC/PCS subsystems, and USB controller IP. OpenFive offers end-to-end expertise in custom SoC architecture, design implementation, software, silicon validation, and manufacturing to deliver high-quality silicon in advanced nodes down to 4nm.
For more information, please visit www.openfive.com.
Related Semiconductor IP
- UCIe RX Interface
- AXI-S Protocol Layer for UCIe
- UCIe PHY (Die-to-Die) IP
- UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
- UCIe D2D Adapter
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- UCIe™ (Universal Chiplet Interconnect Express™) Consortium Releases its 1.1 Specification
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- Leaders in Semiconductors, Packaging, IP Suppliers, Foundries, and Cloud Service Providers Join Forces to Standardize Chiplet Ecosystem
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