OpenFive Launches Die-to-Die Interface Solution for Chiplet Ecosystem
SAN MATEO, Calif., April 5, 2021 – OpenFive, the leading provider of customizable, silicon-focused solutions with differentiated IP, today announced the launch of a Die-to-Die (D2D) PHY that complements the company’s existing D2D Controller to offer complete D2D interface solutions for various packages including substrates and interposers.
The new D2D PHY helps disaggregate large SoC die into smaller die, resulting in better yield, cost and power savings. It features up to 16Gbps NRZ signals with clock forwarding architecture. Each channel, comprising of 40 IOs, can provide effective throughput of up to ~1.75Tbps/mm. Users can stack up multiple channels to further increase overall throughput. The PHY also features built-in PLL, programmable output drivers, and link training state machines.
“The D2D subsystem, including both the controller and PHY, provides best-in-class latency, performance and power profile for various IO, CPU and analog chiplets,” said Ketan Mehta, Sr. Director, Product/Application Marketing, SoC IP, at OpenFive.
“OpenFive’s die-to-die connectivity IP solution will enable widespread integration of proven solutions from chiplet ecosystem partners,” said Mohit Gupta, SVP and GM, SoC IP at OpenFive. “As a custom ASIC and IP provider, OpenFive is well-positioned to provide an entire chiplet solution to our customers at any stage of development, whether it be during design, integration, manufacturing, or testing of Known-Good-Die (KGD).”
For more information, please visit www.openfive.com/ip
OpenFive’s Die-to-Die Parallel IO Interface
About OpenFive
OpenFive, a SiFive Business Unit, is uniquely positioned to deliver highly competitive SoCs with its spec-to-silicon design capabilities, customizable IP for AI/Cloud/HPC/storage/networking applications, and processor agnostic domain-specific architectures. The OpenFive IP portfolio includes High-Bandwidth Memory (HBM2/E), Die-to-Die (D2D) interface IP for multi-die connectivity including chiplets, low-latency, high-throughput Interlaken interface IP for chip-to-chip connectivity, 400/800G Ethernet MAC/PCS subsystems and USB controller IP.OpenFive offers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon in advanced nodes down to 5nm. For more information, please visit openfive.com.
Related Semiconductor IP
- Die-to-Die PHY
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
- TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY
- TSMC CLN5FF GLink 2.0 Die-to-Die PHY
- TSMC CLN5FF GLink 2.3LL Die-to-Die PHY
Related News
- OpenFive Enhances Differentiated IP Portfolio with Die-to-Die Interface Controllers for HPC and Chiplet Markets
- Chiplet Pioneer Eliyan Joins UCIe and JEDEC Industry Standardization Organizations, Expands Veteran Leadership Team to Accelerate Adoption of Breakthrough Die-to-Die Interconnect Solution
- OpenFive and AnalogX to Provide Optimized Chip-to-Chip Interface IP Solutions
- Blue Cheetah Bunch-of-Wires (BoW) Chiplet Interface Solution Targets Rapid Flexibility, Scalability, and Low Overhead
Latest News
- SEALSQ and IC’Alps Unify Expertise to Deliver Integrated Post-Quantum Cybersecurity and Functional Safety for Autonomous Vehicles
- PUFsecurity’s PUFrt Anchors the Security of Silicon Labs’ SoC to Achieve the Industry’s First PSA Certified Level 4
- The next RISC-V processor frontier: AI
- PQShield joins EU-funded FORTRESS Project: Pioneering Quantum-Safe Secure Boot for Europe’s Digital Future
- PQSecure Achieves NIST CAVP Validation