Open-Silicon Strengthens Patent Portfolio with Test Technology
TestMAX’s Scan-Frequency Scaling technology reduces test time and device cost
MILPITAS, Calif. – November 9, 2010 -- Open-Silicon, Inc., a leading ASIC design and semiconductor manufacturing company, announced today that the United States Patent and Trademark Office has issued U.S. Patent 7,805,648 related to Open-Silicon’s TestMAX technology. As a part of Open-Silicon’s custom silicon solution, scan-frequency scaling reduces silicon test time providing customers with an additional way to decrease overall device cost.
Introduced in 2009, TestMAX is part of Open-Silicon’s MAX Technologies product line – a result of extensive R&D to create a series of products that allow customers to take their designs to a level beyond what the latest EDA tools offer. As design gate counts continue to grow exponentially, both wafer probe and final test costs increase. TestMAX addresses this challenge by significantly reducing test time, and therefore lowering device cost. Other significant benefits are that it requires no design changes, is scan-architecture independent, and can be applied on previously taped out designs.
Scan-Frequency Scaling
Traditional scan testing frequencies are limited by the power dissipation in the device under test. By first profiling the scan vectors for power dissipation, Open-Silicon is able to select those tests with lower thermal impact and power mesh currents and greatly increase their frequency.
“The granting of this patent underscores the strength and execution of Open-Silicon’s technology solutions,” said Colin Baldwin, Director of Marketing at Open-Silicon. “Fully custom silicon that wins in the market requires a lot more than today’s readily-available EDA tools. Our team of experienced engineers is focused on solutions that enable the creation of custom silicon that touts optimal power and performance, while reducing cost and accelerating time-to-market.”
About Open-Silicon, Inc.
Open-Silicon, Inc. is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. Open-Silicon’s OpenMODEL brings together Open-Silicon’s engineering technology and high-quality manufacturing services with one of the broadest partner ecosystems for IC development, spanning IC design, open market IP integration, wafer fabrication, and assembly/test services. Open-Silicon received the Global Semiconductor Alliance (GSA) award for Most Respected Private Semiconductor Company in 2008 and 2009. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.
Related Semiconductor IP
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
Related News
- Cassia.ai Achieves Breakthrough in AI Accelerator Technology with Successful Tapeout of two Test Chips
- MoSys Licenses 1T-SRAM-R Embedded Memory to Open-Silicon
- Dr. Edward C. Ross, President Emeritus of TSMC, Joins Open-Silicon Board of Directors
- Open-Silicon Licenses Multiple RaSer Serial Link Cells Under the Cadence-Rambus Reseller Program
Latest News
- CAST Introduces MAC-SEC-MG IP Core for Secure 10G+ Ethernet SoC Designs
- Crypto Quantique and Attopsemi Unite PUF and I-fuse® OTP technology to Deliver Zero-Overhead Device Enrollment on FinFET Technology
- Arasan Announces immediate availability of its UFS 5.0 Host controller IP
- Bolt Graphics Completes Tape-Out of Test Chip for Its High-Performance Zeus GPU, A Major Milestone in Reducing Computing Costs By 17x
- NEO Semiconductor Demonstrates 3D X-DRAM Proof-of-Concept, Secures Strategic Investment to Advance AI Memory