ChipWrights lines up tools, kernel for new DSP-based processor
ChipWrights lines up tools, kernel for new DSP-based processor
By Semiconductor Business News
February 11, 2002 (7:36 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020211S0090
NEWTON, Mass. -- Fabless semiconductor startup ChipWrights Inc. here today announced it has licensed compiler and debugger technology from Metrowerks, a development tool supplier owned by Motorola Inc., for use with its new DSP-based processor. ChipWrights is developing digital signal processing (DSP) solutions based on a "very dense instruction word" architecture, which the company calls VDIW. This architecture includes multiple 32-bit fixed-point imaging DSP engines and a tightly integrated 32-bit RISC processor. The VDIW architecture is fully pipelined and issues one complex SIMD (single instruction, multiple data) instruction per cycle, according to the two-year-old Boston area company. ChipWrights' CWvx architecture is targeted at image and video processing applications, such as battery-powered digital cameras and mobile communications devices. The licensing pact between ChipWrights and Metrowerks is part of a broader partnership to pr ovide a software development kit for the new DSP-based processor. The kit will be based on Metrowerks' CodeWarrior technology. "ChipWrights' license of our CodeWarrior technology allows them to create a compiler and debugger optimized for their architecture," said Berardino E. Baratta, chief technology officer of Metrowerks in Austin, Tex. The agreement is an example of how customers are using CodeWarrior technology to build custom tool sets, he added. Separately, ChipWrights today also announced that Accelerated Technology Inc.'s real-time kernel, called Nucleus Plus, will support its new DSP-based processor. ATI, based in Mobile, Ala., provides real-time operating system kernels for task management, inter-task communication, inter-task synchronization, memory management, and component query features.
Related Semiconductor IP
- Specialized Video Processing NPU IP for SR, NR, Demosaic, AI ISP, Object Detection, Semantic Segmentation
- Ultra-Low-Power Temperature/Voltage Monitor
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
Related News
- Synopsys Acquires RISC-V Processor Simulation Tools Firm
- MosChip® selects Cadence tools for the design of HPC Processor “AUM” for C-DAC
- 3DSP lines up software development support from India's Wipro
- Mentor comms cores take aim at Xilinx FPGA lines
Latest News
- Siemens accelerates integrated circuit design and verification with agentic AI in Questa One
- Weebit Nano achieves record half-year revenue; licenses ReRAM to Tier-1 Texas Instruments
- IObundle Releases Open-Source UART16550 Core for FPGA SoC Design
- Rapidus Secures 267.6 Billion Yen in Funding from Japan Government and Private Sector Companies
- DNP Invests in Rapidus to Support the Establishment of Mass Production for Next-Generation Semiconductors