Chips&Media Secures Access to TSMC 3nm Library
Seoul, South Korea – November 18, 2024 -- Chips&Media has secured a solution to help the customers’ 3nm design with the actual synthesis data.
Chips&Media, a global leader in video IP, officially announced on Nov 6 that it gained access to TSMC’s 3nm library. This enables the company to synthesize and test its IP at the 3nm process node in addition to the existing 5nm of TSMC.
The library test allows customers to evaluate the implementation size of Chips&Media’s IP within TSMC's processes before contracting, further enhancing convenience and efficiency in chip development.
Chips&Media in TSMC Open Innovation Platform (OIP) Ecosystem

Image provided by TMSC (Chips&Media’s logo in the second line, sixth from the left)
"Only TSMC IP Ecosystem partners are eligible to receive the library, and we anticipate gaining access to the soon-to-be-developed 2nm libraries as well because advanced process technologies continue to evolve rapidly. As a longstanding OIP and IP Alliance partner of TSMC, we have actively participated in TSMC's technical symposiums in the United States and have been recognized for our technical expertise," stated Chips&Media.
TSMC’s OIP is a groundbreaking technological infrastructure across semiconductor design and manufacturing. It plays a crucial role in lowering design barriers and increasing the success rate of initial silicon production. By leveraging TSMC’s IP, design implementation, and design for manufacturability (DFM) solutions, customers and partners within the semiconductor design ecosystem are accelerating their adoption of new technologies and reducing the time from design to mass production, market-entry and revenue generation.
In particular, the IP Alliance Program, a key component of OIP, continues to expand and fortify TSMC’s IP ecosystem through partnerships with leading global IP companies offering silicon-proven and production-ready IP.
Sang-Hyun Kim, CEO of Chips&Media, commented, "With the rapid growth of the AI semiconductor market, the partnership between Chips&Media and TSMC is becoming increasingly critical. As an OIP partner of TSMC, we are committed to strengthening our leadership in the AI semiconductor market and driving growth through continuous technological innovation.”
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- TSMC 3nm (N3E) 1.8V SD/eMMC IO
- TSMC 3nm UCIe-A 32G Die to Die Interface
- TSMC 3nm HBM3-8.6G PHY
Related News
- Samsung Foundry Certifies Synopsys PrimeLib Unified Library Characterization and Validation Solution at 5nm, 4nm and 3nm Process Nodes
- Samsung Foundry Adopts Cadence Liberate Trio Characterization Suite for 3nm Production Library
- Alphawave Semi Launches Industry's First 3nm UCIe IP with TSMC CoWoS Packaging
- Unveiling the Availability of Industry's First Silicon-Proven 3nm, 24Gbps UCIe™ IP Subsystem with TSMC CoWoS® Technology
Latest News
- EU DARE Project Is Scrambling to Replace Codasip
- Sofics and Alcyon Photonics Partner to Support Next-Generation Photonic Systems
- QuickLogic Appoints Quantum Leap Solutions as Authorized Sales Representative
- Cadence and NVIDIA Expand Partnership to Reinvent Engineering for the Age of AI and Accelerated Computing
- Cadence and Google Collaborate to Scale AI-Driven Chip Design with ChipStack AI Super Agent on Google Cloud