Aware Announces the complete physical instantiation of its standard-compliant ADSL, ADSL2, and ADSL2+ core IP in the form of a single digital chip
BEDFORD, MA – May 1, 2003 – Aware, Inc. (NASDAQ: AWRE), a worldwide leader and innovator of broadband intellectual property, today announced the immediate availability of its StratiPHY2+™ chip. The StratiPHY2+ is a complete physical instantiation of Aware's standard-compliant ADSL, ADSL2, and ADSL2+ core IP in the form of a single digital chip. StratiPHY2+ delivers downstream data rates of up to 24 Mbps, and interoperates with ADSL and ADSL2 equipment. As an essential wide area network (WAN) interface for broadband silicon providers, StratiPHY2+ is the second offering in a line of completely functional, manufacturable silicon IP offerings from Aware.
“With the addition of StratiPHY2+, Aware’s semiconductor customers have access to a working ADSL2+ silicon platform along with a complete turnkey package of RTL and firmware,” said Luke Smithwick, Aware’s vice president of business development. “This powerful combination of a complete IP platform and a physical chip reduces development costs and time-to-market. StratiPHY2+ can also be used in a packaged chip or bare die form for very rapid market entry strategies.”
Aware’s new StratiPHY2+ offering allows silicon providers to combine Aware’s ADSL IP with the strength and diversity of their existing silicon product offerings to dramatically expand their market and revenue opportunities as well as create entirely new market opportunities that traditional ADSL chipset providers cannot address.
In addition to expanding the market opportunities for existing offerings, StratiPHY2+ provides complete independence from potentially competitive third party ADSL silicon providers, because of its availability from an independent source of intellectual property and its ease of integration into a variety of silicon products. StratiPHY2+ has a robust feature set that implements all required and optional ADSL2+ requirements, as well as legacy ADSL standards, to address the rapidly growing worldwide ADSL market.
Aware has also developed an end-to-end connectivity demonstration for ADSL2+ using StratiPHY2+ and a real-time central office (CO) development platform. Aware's test environment provides a platform to demonstrate the value of ADSL2+ features, as well as providing positive assurance to customers of the high quality of Aware's ADSL2+ intellectual property. The StratiPHY2+ chip is implemented in 0.18 micron CMOS technology and was fabricated at TSMC.
A demonstration of StratiPHY2+ will take place in Aware’s booth (#22261) at SuperComm 2003, which takes place in Atlanta, GA June 2 – 4, 2003. For more information on StratiPHY2+ or any of Aware’s products, please visit Aware’s booth at SuperComm, or Aware’s website at: http://www.aware.com.
About ADSL2+
ADSL2+ (also known as G.992.5) is the new standard consented by the ITU in January 2003. It is based on ADSL2 (G.992.3) and doubles the maximum frequency used for downstream data transmission from 1.1 MHz to 2.2 MHz. As a result, downstream data rates are increased to up to 24 Mbps on phone lines as long as 3,000 feet, and 20 Mbps on lines as long as 5,000 feet.
About Aware
Aware, Inc. designs, develops, licenses and markets DSL technology that enables broadband communications over existing telephone networks. Its solutions, including splitterless G.lite, full-rate ADSL, ADSL2, ADSL2+, VeDSL™, Dr. DSL®, StratiPHY™, StratiPHY2+™, FastADSL™, BondedADSL™, and G.shdsl address central office as well as customer premise requirements. More information about Aware can be found at http://www.aware.com.
Safe Harbor Warning
Portions of this release contain forward-looking statements regarding future events and are subject to risks and uncertainties, such as estimates or projections of future revenue and earnings and the growth of the DSL market. Aware wishes to caution you that there are factors that could cause actual results to differ materially from the results indicated by such statements. These factors include, but are not limited to: we have a unique business model, our quarterly results are difficult to predict, we depend on a limited number of licensees, we derive a significant amount of revenue from one customer, we depend on equipment companies to incorporate our technology into their products, we face intense competition from other DSL vendors, DSL technology competes with other technologies for broadband access, and our business is subject to rapid technological change. We refer you to the documents Aware files from time to time with the Securities and Exchange Commission, specifically the section titled Factors That May Effect Future Results in our annual report on Form 10-K for the year ended December 31, 2002 and other reports and filings made with the Securities and Exchange Commission.
###
VeDSL, Dr. DSL, XRDSL, StratiPHY, StratiPHY2+, FastADSL, and BondedADSL are trademarks or registered trademarks of Aware, Inc. Any other trademarks appearing herein are the property of their respective owners.
Related Semiconductor IP
- JESD204D Transmitter and Receiver IP
- 100G UDP IP Stack
- Frequency Synthesizer
- Temperature Sensor IP
- LVDS Driver/Buffer
Related News
- Aware, Inc announces availability of ADSL2 intellectual Property Solutions
- Aware Announces StratiPHY Chip - The Industry's Most Advanced ADSL2 IP Offering
- Aware, Inc. Commends Completion of the New ADSL2+ Standard
- Aware to Demonstrate DSL Leadership at SuperComm 2003 - The first live demonstrations of ADSL2 features and Reach-Extended ADSL2 highlight this year’s event
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers