Analog Drives Processor Architecture
Nick Flaherty, Embedded Editor, EE Times Europe
10/3/2013 11:36 AM EDT
The recent port of a number of mixed signal interface IP blocks to 20nm by Synopsys Inc raises some fascinating questions on the microprocessor ecosystem. In days gone by, analog was well behind the curve. Now, USB, DDR, PCI Express, and MIPI PHY interfaces are available at what is pretty much the leading edge.
The Synopsys' EM family provides highly configurable cores where instructions can be added to accelerate specific applications -- ideal as the controller for memory or an interface that doesn't have to worry about running an operating system. This makes them well suited to the interfaces that have been ported to TSMC's 20SoC process.
To read the full article, click here
Related Semiconductor IP
- USB Super-speed+ PHY
- USB 20Gbps Device Controller
- USB 2.0 HS PHY Interface
- USB 1.1 Device Controller
- USB Full Speed Transceiver
Related News
- CEVA NeuPro-M Edge AI Processor Architecture Recognized at EE Awards Asia 2022
- The Future of Mobility: Fraunhofer IPMS drives the Revolution in Vehicle Architecture
- RED Semiconductor announces VISC™ licensable high performance processor architecture for RISC-V
- C-DAC partners with MosChip and Socionext for design of HPC Processor AUM based on Arm architecture
Latest News
- NEO Semiconductor Demonstrates 3D X-DRAM Proof-of-Concept, Secures Strategic Investment to Advance AI Memory
- M31 Collaborates with TSMC to Achieve Tapeout of eUSB2V2 on N2P Process, Advancing Design IP Ecosystem
- Menta’s eFPGA Technology Adopted by AIST for Cryptography and Hardware Security Programs
- Silicon Creations Celebrates 20 Years of Global Growth and Leadership in 2nm IP Solutions
- TSMC Debuts A13 Technology at 2026 North America Technology Symposium