RED Semiconductor announces VISC™ licensable high performance processor architecture for RISC-V

April 4, 2024 -- RED Semiconductor (“RED”) announces VISC, an algorithmic microprocessor ISA (Instruction Set Architecture) and hardware design that extends the capabilities of RISC-V for Edge AI, autonomy and cryptography.

VISC is an accelerated RISC-V microprocessor core, which optimises complex mathematical algorithms for parallel execution in its reconfiguration hardware engine. The performance boost delivered by VISC, compared with standard RISC-V, is in demand for the era of ubiquitous AI and the associated exponential increase in data.

The VISC ISA enables developers to describe complex algorithms in just a fraction of the code size it would take with the standard RISC-V instruction set, RISC-V vector extensions, or other ISA like x86 and Arm. VISC hardware decompresses an entire algorithm and sequences execution of elements for optimised parallel execution. Together, the VISC ISA and hardware can deliver over 100x execution benefit in terms of algorithmic performance per unit of power consumed, and its Single-Issue Multi-Execute (SiMex™) architecture optimises performance for silicon area.

Says RED Semiconductor CEO, James Lewis: “RISC-V has the potential to be the architecture of choice for ubiquitous edge AI, in the same way that Arm became the architecture for smartphones. To do so, it needs a differentiated, powerful hardware approach that can perform AI calculations much more efficiently. RED is at the forefront with VISC, a RISC-V-based approach that radically streamlines algorithmic processing to deliver faster, smaller, and lower power edge AI solutions. VISC delivers the performance benefits of dedicated hardware accelerators with the versatility of a general-purpose microprocessor. For SoC developers, it enables multiple heterogeneous compute functions to be accomplished with a unified instruction set and hardware core.”

Says Jon Peddie, president, Jon Peddie Research: “RED Semiconductor could hit RISC-V at that inflection point when it’s just taking off, giving them the opportunity of becoming a key performance accelerator for the RISC-V community. VISC has the potential to reshape heterogenous SoC design for segments like edge AI, much as GPUs have done in the smartphone market, becoming a significant driver of value.”

Inside VISC

The VISC execution architecture is created as a fully functional stand-alone RISC-V compatible core, highly suited to use in ASICs and FPGAs. It has outstanding memory efficiency, eliminating memory accesses during computation for enhanced security. Its versatility to run general purpose compute functions, operating systems, mathematical acceleration, signal processing and graphics functions means it can be used as a co-processor or for all functions in heterogenous computing SoCs.

RED’s approach to algorithmic processing for RISC-V uses a precoding system that enables RISC-V scalar instructions to be parallelised. VISC’s registers, decoders, and execution engine are all optimised for efficient parallel computation of complex repetitive functions like FFT (Fast Fourier Transform), DCT (Discrete Cosine Transform), Matrix Multiplication, and Big Integer Maths. Exponentially improving the efficiency of these functions is the key to enabling ubiquitous and secure AI compute. A VISC enabled RISC-V processor can quickly handle large volumes of data, enabling data-heavy applications such as AI inferencing, high-performance computing, real time analytics and video streaming.

VISC delivers 100x code densification, execution performance boost and power reduction. On top of that, VISC has remarkable code density – a matrix multiply takes only three instructions, for example, which compares with 100+ for today’s mainstream ISAs. VISC is scalable from one to >1,000 cores enabling everything from edge to HPC (High Performance Computing) hyperscale applications. While currently implemented for RISC-V, VISC is fundamentally ISA agnostic, and RED Semiconductor may apply it to other instruction set architectures in the future.

The VISC architecture delivers a step change in execution performance. It contains a Decompression Engine that simultaneously decodes code, and accelerates issue to execution units, enabling multi-execution from a single-issue pipeline. Then an Execution Optimisation Engine deterministically orders and executes up to 16 parallel instructions. VISC’s Versatile Deep Register Set, accessible by all instruction types, enables execution of complex routines in registers, eliminating cache misses. All processing is kept in the core until the routine has been executed, reducing hack-attack surfaces.

Continues Lewis: “Market predictions from SHD Group say that by 2030, 16 billion SoCs would use RISC-V cores. We believe this is entirely attainable, but requires differentiation in performance, security, and design methodology. We are already establishing partnerships with RISC-V, cryptography, and tools companies to deliver a compelling solution that can turn a RISC-V processor design into an AI powerhouse.”

VISC enables processors for a wide range of markets where algorithmic processing is increasingly in demand, including: aerospace; AI/ML; AR/VR; autonomy; critical infrastructure; fintech; healthtech; high-performance computing; and industry 4.0.

RED Semiconductor is part of the first cohort of ChipStart UK, the government-backed incubator launched through the National Semiconductor Strategy and run by Silicon Catalyst UK.

RED Semiconductor’s mission is to develop and deliver a new class of algorithmic microprocessor IP optimised for RISC-V that enables complex computational routines to be performed in fewer clock cycles, with smaller binaries, and consuming less power than traditional RISC architectures. See: redsemiconductor.com