UltraScale+ Device Integrated Block for PCI Express (PCIe)
The Xilinx® UltraScale+ FPGA Integrated Block for PCI Express® solution IP core is a high-bandwidth, scalable, and reliable seria…
PCIe 3.1 PHY (6nm, 7nm, 12nm, 14nm, 16nm, 22nm, 28nm and 40nm)
M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
Multiprotocol 10G PHY, TSMC N7 x2, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, TSMC 16FFPLL x8, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
Multiprotocol 10G PHY, TSMC 16FFC x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G MP PHY for PCIe 3.0/USXGMII/SGMII, TSMC 12FFC x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, SS SF5 x2, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, SS SF5 x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
Multiprotocol 10G PHY, SS 8LPU x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
MP10, USB 3.1/PCIe 3.0 PHY, GF 22FFDSOI x1, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 1
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G Multi-Protocol PHY, GF 22FDSOI x1, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 1
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
PCIe Gen4 PHY, x1-lane, RC/EP, TSMC 16FFC, N/S orientation
The PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
PCIe Gen4 PHY, x4-lane, RC/EP, TSMC 16FFC, N/S orientation
The PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
PCIe Gen4 PHY, x1-lane, RC/EP, TSMC 12FFC, N/S orientation
The PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
PCIe Gen4 PHY, x4-lane, RC/EP, TSMC 12FFC, N/S orientation
The PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
PCIe Gen4 PHY, x2-lane, RC/EP, TSMC N7, 1.8V, N/S orientation
The PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
PCIe Gen4 PHY, x2-lane, RC/EP, TSMC N6, 1.8V, N/S orientation
The PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
PCIe 4.0 PHY in TSMC(6nm,7nm, 12nm,16nm)
M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.