100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 80…
As serial link speeds have increased, the reach achievable has become more and more limited by the lossy nature of the physical m…
Ethernet 40G,100G Verification IP
The Ethernet 40G,100G Verification IP is compliant with IEEE 802.3ba and IEEE 802.3bj specifications and verifies MAC-to-PHY and …
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 supporting…
UltraScale+ Integrated 100G Ethernet Subsystem
Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC), Physical Coding Sublayer (PCS),…
IEEE 802.3bj Reed-Solomon Forward Error Correction
Xilinx® offers the 100 Gigabit IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise…
Ethernet - up to 800G Verification IP
The 10/100/1G/2.5G/5G/10G/40G/100G/200G/400G/800G Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifi…
The Ethernet-TSN Verification IP is compliant with IEEE 802.3 specification.
KMX 100G MAC and PCS core, which consists of media access control (MAC) module, physical coding sublayer (PCS) module and physica…
Ethernet Synthesizable Transactor
The Ethernet Synthesizable Transactor verifies Ethernet interfaces.
Ethernet 100G Synthesizable Transactor
The Ethernet 100G Synthesizable Transactor verifies Ethernet interfaces.