6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as s…
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi…
Standard Cell Library in SkyWater 90nm
A low-leakage digital standard cell library for energy-efficient, long-lifecycle SoC designs in SkyWater 90nm CMOS.
Specialty SSTL IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic Library (core) 1.8V MDDR IO with POC (Pad On Circuit).
SMIC 0.13um Generic UHD RVT Logic standard cell library.
SMIC 0.13um Generic UHD LVT(6T) Logic standard cell library.
SMIC 0.13um Generic UHD LVT(6T) Logic standard cell library.
SMIC 0.13um Generic UHD HVT(6T) Logic standard cell library.
SMIC 0.13um Generic UHD HVT(6T) Logic standard cell library.
SMIC 0.13um Low Leakage high density RVT Logic standard cell library.
SMIC 0.13um Low Leakage UHD RVT Logic standard cell library, compatible with E-Flash and EEPROM process.
SMIC 130nm G SSTL2 and LVTTL combo I/O library
IP
SMIC 130nm G SSTL2 I/O library
IP
SMIC 130nm G Mobile DDR I/O library
IP
VeriSilicon SMIC 0.18μm 1.8V/3.3V CFIO_01 Library
VeriSilicon SMIC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for SMIC 0.18μm 1P6M Salicide logic proces…
The SMBus library provides open-drain bi-directional I/O cells designed for the High-Power SMBus two-line interface.
The I2C library provides open-drain bi-directional I/O cells designed for the I2C two-line interface.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm LL process
UMC 90nm LL/HVT Low-K Logic process Cell Library POWERSLASH Core Cell Library (high density Version).
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process UHS Library POWERSLASH cells.
VeriSilicon UMC 0.18μm CF I/O
VeriSilicon UMC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for UMC 0.18μm 1.8v/3.3v 1P6M Generic II lo…
VeriSilicon UMC 0.18μm CF I/O
VeriSilicon UMC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for UMC 0.18μm 1.8v/3.3v 1P6M Generic II lo…
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 90nm LL process
UMC 90nm LL/HVT Low-K Logic process Cell Library (high density Version).