PCIe Gen 6 Phy
- Multi-Protocol PHY
PCIe Gen 6 Phy
The PCIe Gen 6 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 6 interfa…
PCIe Gen 6 controller IP
Truechip's CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of a…
CXL 4.0/3.2/3/2 Verification IP
The CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP or…
The PCIe Switch Verification IP provides an effective & efficient way to verify the components interfacing with the PCIe Switch i…
The PCIe Gen 5 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 5 interfa…
Our latest PCIe gen 6 controller IP, which is "NoC aware", provides a high-speed interface for efficient data transfer and system…
1-56Gbps Serdes - 7nm (Multi-reference Clock)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Ultra Low Latency)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Area-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (PPA-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
PCIE Gen6 digital controller (Dual Mode)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.
PCIE Gen6 digital controller (Root Complex)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.
PCIE Gen6 digital controller (End Point)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.
The PCIe PHY IP supports PCIe Gen 4.0, 5.0, and 6.0, and is validated through interoperability testing in collaboration with glob…
The AXI Bridge for PCIe IP core is the IP solution with a mix of multiple industry standard memory mapped AXI Interfaces.The AXI …
AXI Bridge with DMA for PCIe IP Core
The AXI Bridge with DMA IP core is the ultimate PCIe DMA IP solution with a mix of multiple industry standard AXI Interfaces.