Pixel processor - High Image Quality Super Resolution
The SR2000 series IPs are silicon-proven, super resolution designs for smart display.
The VC9800D enables up to 256 streams decoding with robustness, high throughput single-core solution, or multi-core solution, sup…
Hantro VC9800E enables up to 256 streams encoding with high video quality single-core solution, or multi-core solution, supportin…
ACAP HDR Image Signal Processing Framework
The ACAP HDR Image Signal Processing Framework is intended to showcase a logicBRICKS IP suite implementation of High-Dynamic Rang…
40nm 1.8V Programmable 1.1V LDO Regulator with 50mA max. output
The TRV702TSM40LP IP is a 1.8V low-power programmable 1.1V LDO implemented in TSMC Low-Power 40nm CMOS process technology.
40nm 1.8V Programmable Band-Gap Reference with 0.55V output
The TRV701TSM40LP IP is a 1.8V low-power low-noise programmable 0.55V Band-Gap Reference implemented in TSMC Low-Power 40nm CMOS …
40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
The TRV401TSM40LP IP is a 1.1V low-power low-silicon-area AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Fractional-N Clock-PLL.
40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
The TRV301TSM40LP IP is a 1.1V low-power low-silicon-area 16MHz-to-2GHz Fractional-N Clock PLL implemented in TSMC Low-Power 40nm…
12-bit 40nm 1.1V 64MHz-to-340MHz continuous-time Delta-Sigma ADC
The silicon-validated TRV103GFY40LP IP is a 1.1V low-power 12-bit 64MHz-to-340MHz continuous-time Delta-Sigma ADC with OSR of 32 …
ECC7 Elliptic Curve Processor for Prime NIST Curves
Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curve…
RSA2-AHB Accelerator Core with AHB Interface
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponen…
AES Mutli-Purpose crypto engine
The AES Multi-Purpose crypto engine includes a generic and scalable implementation of the AES algorithm and a configurable wrappe…
The programmable Fractional-N PLL to lock to an incoming clock source and produce an output clock with a non-integer multiplicati…
Scalable RSA and Elliptic Curve Accelerator
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponen…
HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol.
True Random and Pseudorandom Number Generator
The true random generator core implements true random number generation.
Cryptographically Secure Pseudo Random number Generator IP Core
The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90.
130nm FTP Non Volatile Memory for Standard CMOS Logic Process
NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot …
130nm OTP Non Volatile Memory for Standard CMOS Logic Process
NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot …
90nm FTP Non Volatile Memory for Standard CMOS Logic Process
NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot …