Overview
The TRV702TSM40LP IP is a 1.8V low-power programmable 1.1V LDO implemented in TSMC Low-Power 40nm CMOS process technology. Its low noise and high-precision makes it especially suitable for use in wireless communication and broadcast integrated circuit subsystems (LTE, WiFi, WiMAX, DAB, DAB+, FM, HDFM, DRM, etc).
Learn more about LDO Voltage Regulator IP core
Leveraging Tetrivis’ proven KuKa® transceiver IP—already sampling on a 40 nm node for customer demonstrations—the partners will translate the design to an advanced 12 nm process and package it as a UCIe-ready chiplet for next-generation satellite communications, phased-array radar, high-throughput backhaul and secure aerospace links.
Tetrivis LTD, a provider of specialist Analogue, Mixed-Signal, RF and mm-Wave Intellectual Property, has today taped out the TRV003 (Rx) and TRV004 (Tx) RF/mm- Wave Integrated Circuits for fabrication, the first chipsets in the KuKa™ family of Phased Array ASICs.