Synopsys, Inc.
•
HQ:
USA
The DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3, DDR3L (1.3…
- Single-Protocol PHY
Compare 17 LPDDR2 SDRAM Controller IP Listing from 4 vendors
-
-
Dolphin Technology• HQ: USA
Dolphin Technology's hardened DDR5/4/3/2 SDRAM PHY and LPDDR5/4x/4/3/2 SDRAM PHY IP is a silicon-proven.
- Single-Protocol PHY
-
Synopsys, Inc.• HQ: USA
Synopsys offers a system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performanc…
- DDR
- Available on request
- Available
-
Synopsys, Inc.• HQ: USA
Synopsys offers a system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performanc…
- DDR
- Available on request
- Available
-
VeriSyno Microelectronics Co., Ltd.• HQ: The People's Republic of China
The DDR4 multiPHY is a mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a S…
- Single-Protocol PHY
- Silicon Proven
- Immediate
-
SmartDV Technologies• HQ: India
LPDDR2 DFI Verification IP provides an smart way to verify the LPDDR2 DFI component of a SOC or a ASIC.
- Verification IP
-
VeriSyno Microelectronics Co., Ltd.• HQ: The People's Republic of China
The DDR multiPHYs are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 S…
- Single-Protocol PHY
- Silicon Proven
- Immediate
-
Synopsys, Inc.• HQ: USA
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
- Single-Protocol PHY
-
Synopsys, Inc.• HQ: USA
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
- UMC
- 28nm
- HPC
-
Synopsys, Inc.• HQ: USA
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
- TSMC
- 28nm
- HPC+
-
Synopsys, Inc.• HQ: USA
The Gen 2 DDR multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard LPDDR2, LPDDR3…
- Single-Protocol PHY
-
DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
Synopsys, Inc.• HQ: USAThe Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
- DDR
-
Synopsys, Inc.• HQ: USA
The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
- DDR
-
Synopsys, Inc.• HQ: USA
The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
- DDR
-
Synopsys, Inc.• HQ: USA
The Synopsys DDR4 multiPHY is a physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- ch…
- UMC
- 28nm
- HPC
- Available on request
-
Synopsys, Inc.• HQ: USA
The Synopsys DDR4 multiPHY is a physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- ch…
- TSMC
- 28nm
- HPC+
- Available on request
-
DDR4 multiPHY in Samsung (14nm)
Synopsys, Inc.• HQ: USAThe Synopsys DDR4 multiPHY is a physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- ch…
- Samsung
- 14nm
- Available on request