LPDDR IP Listing

LPDDR5X Memory Model provides an smart way to verify the LPDDR5X component of a SOC or a ASIC.

• Controller
• LPDDR5X

LPDDR5 Memory Model provides an smart way to verify the LPDDR5 component of a SOC or a ASIC.

• Controller
• LPDDR5

LPDDR4 Memory Model provides an smart way to verify the LPDDR4 component of a SOC or a ASIC.

• Controller
• LPDDR4

LPDDR5 DFI Verification IP provides an smart way to verify the LPDDR5 DFI component of a SOC or a ASIC.

• Verification IP

LPDDR4 DFI Verification IP provides an smart way to verify the LPDDR4 DFI component of a SOC or a ASIC.

• Verification IP

LPDDR5X Synthesizable Transactor provides a smart way to verify the LPDDR5X component of a SOC or a ASIC in Emulator or FPGA plat…

• Controller
• LPDDR5X

LPDDR5 Synthesizable Transactor provides a smart way to verify the LPDDR5 component of a SOC or a ASIC in Emulator or FPGA platfo…

• Controller
• LPDDR5

LPDDR4 Synthesizable Transactor provides a smart way to verify the LPDDR4 component of a SOC or a ASIC in Emulator or FPGA platfo…

• Controller
• LPDDR4

LPDDR5 DFI Synthesizable Transactor provides a smart way to verify the LPDDR5 DFI component of a SOC or a ASIC in Emulator or FPG…

• Protocol Bridge

LPDDR4 DFI Synthesizable Transactor provides a smart way to verify the LPDDR4 DFI component of a SOC or a ASIC in Emulator or FPG…

• Protocol Bridge

LPDDR4 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR4 JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C,…

• Controller
• LPDDR4

DFI LPDDR5 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5 JESD209-5 specification and DFI-version 5.…

• Controller + PHY + 1
• LPDDR5

LPDDR5X is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5X draft JEDEC specification, JESD209-5B specif…

• Controller
• LPDDR5X

LPDDR5 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5 JESD209-5, JESD209-5A and JESD209-5B specifica…

• Controller
• LPDDR5

LPDDR5 Verification IP (VIP) is a tool designed to simulate and validate the functionality of LPDDR5 memory controllers.

• Controller

In production since 2015 on dozens of production designs.This Cadence® Verification IP (VIP) supports the JEDEC® Low-Power Memory…

• Verification IP
• Controller
• LPDDR5

In production since 2015 on dozens of production designs.This Cadence® Verification IP (VIP) supports the JEDEC® Low Power Memory…

• Verification IP
• Controller
• LPDDR4

With sophisticated architecture and technology, the Vendor provides LPDDR5 IP solution with high performance and low power.

• Controller
• LPDDR5

LPDDR5X Assertion IP provides an efficient and smart way to verify the LPDDR5X designs quickly without a testbench.

• Controller
• LPDDR5X

LPDDR5 Assertion IP provides an efficient and smart way to verify the LPDDR5 designs quickly without a testbench.

• Controller
• LPDDR5