Dual Port SRAM Compiler IP, UMC 65nm LL process
UMC 65nm low leakage RVT Logic Low_K process synchronous high density Dual Port SRAM memory compiler with bist testing interface.
- UMC
- 65nm
- LL
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Dual Port SRAM Compiler IP, UMC 65nm LL process
UMC 65nm low leakage RVT Logic Low_K process synchronous high density Dual Port SRAM memory compiler with bist testing interface.
Dual Port SRAM Compiler IP, UMC 65nm SP process
UMC 65nm 1.0V SP Low-K Logic process synchronous high density Dual Port SRAM compiler (with row redundancy option).
Dual Port SRAM Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous Dual Port RAM memory compiler.
Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process
UMC 55nm 1.0V Standard Performance (SP) Low-K Logic process synchronous, high density, Dual Port SRAM with row redundancy option.
Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process
UMC 55nm SP Low-K Logic process Low Power synchronous high density Dual Port SRAM memory compiler with redundancy.
Dual Port SRAM Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process Low Power synchronous high density Dual Port SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.18um MS process
UMC 0.18um MM/RF process synchronous high density Dual Port SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/RVT Logic process synchronous high density Dual Port SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process synchronous high density Dual Port SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE Logic process synchronous High-density Dual Port SRAM memory compiler.
LVDS Transmitter IP, 8MHz - 135MHz, UMC 90nm SP process
2.5V LVDS Transmitter 8~135MHz, UMC 90nm SP process.
LVDS Receiver IP, 700Mbps, UMC 0.13um SP/FSG process
Low Power LVDS Receiver 700Mbps, UMC 90nm SP/RVT Low-K Logic process.
LVDS Receiver IP, 8MHz - 135MHz, UMC 0.13um SP/FSG process
2.5V LVDS Receiver 8~135MHz, UMC 90nm SP process.
LVDS Transmitter IP, 8MHz - 135MHz, 4 channels, UMC 0.13um SP/FSG process
2.5V 4 channel LVDS Transmitter 8~135MHz, UMC 90nm SP/RVT Low-K process.
LVDS Rx IO IP, UMC 0.18um Logic process
LVDS RX IO, UMC 90nm SP/RVT Low-K Logic process.
LVDS Rx IO IP, 500Mbps, UMC 90nm LL process
Low Power LVDS Receiver IO 500Mbps, UMC 55nm SP/RVT Low-K Logic process.
LVDS Transmitter IP, 16MHz - 178MHz, UMC 55nm SP process
2.5V LVDS Transmitter 16~178MHz, UMC 55nm SP/RVT Low-K Logic process.
LVDS Receiver IP, UMC 90nm SP process
DLL-based LVDS RX, UMC 55nm SP/RVT Low-K Logic process.
LVDS Transmitter IP, 700Mbps, UMC 90nm SP process
2.5V LVDS Transmitter 700Mbps, UMC 55nm SP Low-K Logic process.
LVDS Tx IO IP, UMC 90nm SP process
LVDS TX Pad, UMC 0.35um Logic process.