The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
- UCIe 1.1
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
CSMS 0.13um 5v-3.3v/1.8v Power Regulator
Based on CSMC 0.13um 3.3v/1.2v Logic process, this design of Low-Dropout (LDO) regulator is to provide both 3.3V and 1.2V supplie…
The present IP is a Power On Reset (POR) circuit without any external resistor or capacitor.
CSMC 0.13um Generic Process Programmable Gain Amplifier
The CS13V33_PGA_02 integrates two 2-channel programmable gain amplifiers It is always combined with audio ADC or audio DAC to pre…
This PLL is designed for audio clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
CSMC 0.13um 3.3v RC Oscillator
The present IP is a RC oscillator with internal R and C to generate 32±20%KHz clock.
CSMC 0.13um 32KHz Crystal Oscillator
This is a 32768Hz crystal oscillator specifically designed for ultra-low power application.
CSMC 0.13um 5v-3.3v/1.2v Battery Charger
Based on CSMC 0.13um 3.3V/1.2V Logic process, current design of the Battery Charger IP is a constant current/constant voltage lin…
CSMC 0.13um 8-Bit 4-Input 200k SAR ADC
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 8-bit resolution.
This IP is a programmable Analog PLL suitable for high speed clock generation.
VeriSilicon IBM 65nm 1.0V/2.5V VPPIO_01 IO Library
VeriSilicon IBM 65nm 1.0V/2.5V VPPIO_01 IO library developed by VeriSilicon is optimized for IBM 65nm 10sf 1.0/2.5V process.
SATA Host Controller on Virtex 6 LXT
The LDS SATA HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA.
IBM10LPE 1.2v/2.5v 11bit R2R DAC
The I65LPEV25_R2RDAC_01 is a 11bit 1MHz DAC IP.
This analog 2-1 MUX is designed for low speed application.
Noesis Technologies ntT1_G704 Framer/Deframer is designed for T1 networks and is compliant with ITU recommendations G.704, G.706,…
USB 3.0 OTG PHY IP, UMC 90nm SP process
USB 3.0 Transceiver, UMC 90nm SP/RVT Low-K Logic process.
USB 3.0 OTG PHY IP, UMC 55nm SP process
USB3.0 PHY, UMC 55nm SP/RVT Low-K Logic process.
USB 3.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB3.0 OTG PHY, UMC 0.13um HS/FSG Logic process.
USB 3.0 OTG PHY IP, UMC 0.11um HS/FSG process
USB3.0 PHY, UMC 0.11um HS/FSG (Cu) Logic process.