PLL IP Listing

Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz, frequenc…

• UMC
• 40nm
• LP

Input 12MHz, output 96M~180MHz, 1.08~1.32V frequency synthesizable PLL, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process.

• UMC
• 110nm
• HS

Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um SP/FSG Logic process.

• UMC
• 110nm
• SP

Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um Logic/MIXEDMODE AE process.

• UMC
• 110nm

Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um Logic/MIXEDMODE AE process.

• UMC
• 110nm

Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.

• UMC
• 40nm
• LP

Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process.

• UMC
• 55nm
• LP

Input 10-50MHz, output 10-200MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process(Note:same schematic with FXPLL010HH0…

• UMC
• 40nm
• LP

Input 10-50MHz, output 10-200MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process.

• UMC
• 40nm
• LP

Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL, UMC 0.11um HS/AE Logic process, It has lock detector function.

• UMC
• 110nm
• HS

Input 372M ~ 540MHz, output 5M ~ 420MHz, PLL, UMC 0.11um HS/FSG Logic process.

• UMC
• 110nm
• HS

The S13V33_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplifier,…

• Audio Codec
• Available on request

The S13V33_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplifier,…

• Audio Codec
• Available on request

PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multip…

• SMIC
• 180nm
• G
• Silicon Proven

Granite SemicCom's Digital PLL is intended for applications such the Clock-Multiplying-Unit in a SERDES or a Clock-Driver with fr…

• TSMC
• 40nm
• G

The CMOS high-frequency divider consists of two independent circuits.

• TSMC
• 180nm
• BCDG2
• Silicon Proven

This PLL is designed for audio clock generation.

• PLL
• GDS Ready

Designed for audio clock generation, this PLL integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control …

• IBM
• 65nm
• LPe

This IP is a programmable Analog PLL suitable for high speed clock generation.

• SMIC
• 65nm
• LL

The lock detector monitors the current status of PLL by comparing the phase difference of VCO divided signal and reference oscill…

• PLL
• Pre-silicon verification