SMIC 65nm High-Density Low_vt Standard Library for LL Process.
SMIC 65nm High-Density Low_vt Standard Library for LL Process.
- SMIC
- 65nm
- LL
- In Production
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
SMIC 65nm High-Density Low_vt Standard Library for LL Process.
SMIC 65nm High-Density Low_vt Standard Library for LL Process.
SMIC 65nm High-Density High_vt Standard Library for LL Process.
SMIC 65nm High-Density High_vt Standard Library for LL Process.
65nm LL(LVt) (HD1)High Density standard cell library.HD1 means only M1 used within cell
65nm LL(LVt) (HD1)High Density standard cell library.HD1 means only M1 used within cell
65nm LL(HVt) (HD1)High Density standard cell library. HD1 means only M1 used within cell
65nm LL(HVt) (HD1)High Density standard cell library.
65LL very high speed single-port SRAM compiler with RVT bit cell.
65LL very high speed single-port SRAM compiler with RVT bit cell.
65LL high speed two-port register file compiler with HVT bit cell.
65LL high speed two-port register file compiler with HVT bit cell.
65LL high speed dual-port SRAM compiler with HVT bit cell.
65LL high speed dual-port SRAM compiler with HVT bit cell.
65LL high speed VIA ROM compiler.
65LL high speed VIA ROM compiler.
SMIC 65nm LL 32.768KHz low-power oscillator IO for RTC application
IP
SMIC 65nm LL 32.768KHz oscillator IO
IP
IP
SMIC 65nm LL LPDDR interface for mobile-DDR application
IP
IP
IP
Translation cell between SP65NLLD2P_3P3V library and SP65NLLD2P_MEMIO_COMBO
SMIC 65nm LL Local ESD protection cell
IP
SMIC 65nm LL Standard analog IO
IP
SMIC 65nm LL Standard analog IO
IP
SMIC 65nm LL Standard digital and oscillator IO
IP
SMIC 65nm LL Standard digital and oscillator IO
IP