Standard Cell (Generic) Library IP, UMC 0.13um process
UMC 0.13um Logic process, DFY Cell Library.
- UMC
- 130nm
- HS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Standard Cell (Generic) Library IP, UMC 0.13um process
UMC 0.13um Logic process, DFY Cell Library.
Linear Regulator IP, UMC 0.11um HS/AE process
3.3V to 1.2V Capacitor-Free Linear Regulator with 100mA driving capability, UMC 0.11um HS/AE (AL Enhancement) Logic Process
USB 2.0 Device PHY IP, UMC 0.11um eFlash process
UMC 0.11um eFlash Process , USB 2.0 OTG PHY
1.0~3.6V input, loading 20mA, 0.9V output with VBG=0.75V Linear Regulator, UMC 55nm ULP/UHVT Low-K Logic Process
Input 1.0V-3.6V, VBG=0.75V, Band Gap, UMC 55nm ULP Low-K Logic process
Standard Cell (RTC) Library IP, UMC 55nm ULP process
UMC 55nm ULP/uHVT LowK Logic Process 2.5 V OD 3.3 V device RTC Core Library
Power on Reset IP, Input: 3.3V, Vrr=2.81V, Vfr=2.81V, UMC 55nm SP process
Vrr=2.81V Vfr=2.81V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset,special request, UMC 55nm SP/RVT LowK Logic Process
A/D Converter IP, 10 bits, 54Msps, Pipelined, Single-end Input, UMC 55nm SP process
1.0V/3.3V 10Bits 54MSPS Single-end Input Pipelined ADC, UMC 55nm SP, LowK, Logic Process
Ring Oscillator IP, Output: 32KHz, UMC 55nm LP process
Internal-RC and Built-in Bandgap, trimmable fixed frequency 80MHz with trimming pad.
MIPI M-PHY IP, UMC 40nm LP process
MIPI MPHY 6Gbps/lane, UMC 40nm LP Low-K process.
LVDS RX, UMC 40nm LP/RVT Low-K Logic process.
ROM Compiler IP, UMC 28nm HPC process
UMC 28nm HPC process Via ROM compiler
A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.11um HS/FSG process
10bit 1MSPS SAR ADC with 8-to-1 Mux , UMC 0.11um HS/FSG Logic Process
64-bit Initiator/Target for PCI-X & 32- and 64-bit Initiator/Target for PCI
DO-DI-PCIX64-VE rolls the Initiator/Target for PCI ™/PCI-X ™, 32-bit Initiator/Target for PCI and 64-bit Initiator/Target for PCI…
With this core, the Xilinx Universal Serial Bus 2.0 High Speed Device provides a control interface to internal registers via a 32…
The Xilinx® LogiCORE™ IP JESD204 PHY core implements a JESD204B physical interface to simplify sharing serial transceiver channel…
GSMC 0.13um LP process 1.2v/3.3v Generic IO library
GSMC 0.13um process 1.2v/3.3v Generic IO library
M31 Digital PLL IP in 3nm, 5nm, 6nm, 7nm, 12nm, 16nm, 22nm,28nm,40nm
M31 Digital PLL is a core-power only programmable phase-locked loop (PLL) for frequency synthesis.
PCIe 2.1 PHY(12nm,14nm, 16nm, 28nm, 40nm, 55nm)
M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.