OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
- UMC
- 55nm
- LP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM AFE using UMC 55nm eFlash Process
OFDM AFE using UMC 55nm eFlash Process
Analog Front End IP for CMOS image processing applications
FXAFE010HF0A is an Analog Front End IP for CMOS image processing applications.
UMC 40nm high performance mono audio codec with highly integrated analog functionality system
UMC 40nm high performance mono audio codec with integrated analog functionality system
UMC 28nm high performance stereo audio codec with highly integrated analog functionality system
UMC 28nm high performance stereo audio codec with integrated analog functionality system
a 10-bit 1-MSPS 11-to-1 SAR-ADC with 11-channel GPIO integrated based on UMC 55nm eFlash process
a 10-bit 1-MSPS 11-to-1 SAR-ADC with 11-channel GPIO integrated based on UMC 55nm eFlash process
a 12-bit 1MSPS SAR-ADC on UMC 40nm LP, with 10-channel GPIO integrated
a 12-bit 1MSPS SAR-ADC on UMC 40nm LP, with 10-channel GPIO integrated
0.9V/1.8V 9Bits 125MSPS Pipelined ADC; UMC 28nm HPC+, LowK, Logic Process
0.9V/1.8V 9Bits 125MSPS Pipelined ADC; UMC 28nm HPC+, LowK, Logic Process
125M 9bit 2.5bit pipeline share-OP ADC for 10/100/1000 Ethernet DPHY use; UMC 28nm HPC/Low-K process
A 12bit 2Msps low power and large voltage range SAR-ADC based on UMC 55nm eflash process
A 12bit 2Msps low power and large voltage range SAR-ADC based on UMC 55nm eflash process
Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process
Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS/200KSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS/200KSPS single-end SAR A/D Converter; UMC 28nm HPC process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP eflash process (GPIO Function integrated)
12Bit 1Msps SAR-ADC based on UMC 55nm uLP eflash process (GPIO Function integrated)
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS SAR A/D Converter; UMC 28 nm HPC process
10 bit 1MSPS SAR A/D Converter; UMC 28 nm HPC process