The S8051XC3 IP core implements a high-performance, low-energy, 8-bit microcontroller that executes the MCS®51 instruction set an…
- MCU
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The S8051XC3 IP core implements a high-performance, low-energy, 8-bit microcontroller that executes the MCS®51 instruction set an…
Implements MIL-STD-1553 serial data bus.
DO-254 Soft Error Mitigation Controller 1.01a
The Soft Error Mitigation (SEM) IP core performs SEU detection, correction, and classification.
SATA Device Controller on Kintex 7
The LDS SATA 3 DEVICE XK7 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex…
Multi-Video-Source Multiplexing Serial Video Transmitter for MIPI CSI2
The SVT-CS4AP2 supports MIPI CSI2 over MIPI D-PHY.
triple-speed (10Mbps/100Mbps/1Gbps) Ethernet controller
The Flexibilis Ethernet Controller (AFEC) is a triple-speed (10Mbps/100Mbps/1Gbps) Ethernet controller IP block that can be emplo…
The I2C-MS core is a controller for the Inter-Integrated Circuit (I2C) bus.
CAN CC, CAN FD, and CAN XL Bus Controller
The CAN-CTRL implements a featured and reliable CAN bus controller that performs serial communication according to the Controller…
Single Port Register File compiler - TSMC 110 nm HV_1.5V_5V_32V - Memory optimized for ultra high density and high speed - compil…
USB3.0 Superspeed OTG Controller
WWAGO USB3.0 SS-OTG controller IP is compliant with OTG&EH3.0.
Multiple - Time Programmable Non-Volatile Memory
YMC’s embedded MTP IP owns multiple times of program/erase operation,adopting logic-based structure,and easily ported to differen…
Gigabit Ethernet Media Access Controller
Implements an Ethernet Media Access Controller compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specification…
ColdFire V1 core with AMBA peripherals connected in a subsystem
The ColdFire® V1 Platform (CFV1P) is a fully configurable micro controller subsystem built from the same ColdFire V1 processor IP…
Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 256 k
Foundry Sponsored - Metal programmable ROM compiler - TSMC 130 nm BCD - Non volatile memory optimized for low power - compiler ra…
Single Port SRAM compiler - TSMC 55 nm LPeF - Memory optimized for high density and Low power - compiler range up to 320 k
Single Port SRAM compiler - TSMC 180 nm uLL - Memory optimized for ultra low power and high density - Dual Voltage - compiler ran…
Foundry Sponsored - Single Port Register File compiler - TSMC 110 nm HV_1.5V_5V - Memory optimized for ultra high density and hig…
IEEE 1588 Boundary, Slave And Master Clock
The IPC9004 utilizes IPClock’s technology for IEEE 1588 v2 optimized for providing high quality frequency synchronization and Tim…
IEEE 1588 Boundary, Slave And Master Clock
The IPC9010 utilizes IPClock’s IEEE 1588 v2 technology optimized for providing high quality frequency synchronization and Time of…
IEEE 1588 Boundary, Slave And Master Clock
The IPC9006 utilizes IPClock’s IEEE 1588 v2 technology optimized for providing high quality frequency synchronization and Time of…