6-bit, 1 GSPS High Performance AFE in 28nm CMOS
The ODT-AFE-6B1G-28HPCPT is a high-performance I/Q ADC and I/Q DAC designed in a 28nm CMOS process.
- TSMC
- 28nm
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
6-bit, 1 GSPS High Performance AFE in 28nm CMOS
The ODT-AFE-6B1G-28HPCPT is a high-performance I/Q ADC and I/Q DAC designed in a 28nm CMOS process.
14-bit, 1200 MSPS Ultra Low Power AFE in 28nm CMOS
The ODT-AFE-14B1P2G-28 is a low power high speed pipelined AFE designed in a 28nm standard CMOS process.
Network Redundancy (HSR & PRP) core
The HSR&PRP Core from NetTimeLogic is a standalone Network Redundancy Core according to IEC62439-3 rev3.
Radio Clock (DCF77) Master core
NetTimeLogic’s DCF Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other…
Radio Clock (DCF77) Slave core
NetTimeLogic’s DCFSlave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a DC…
Real Time Clock (RTC) Master core
NetTimeLogic’s RTC Master Clock is a full hardware (FPGA) only implementation of a synchronization core allowing to read and writ…
NMEA Time of Day (ToD) Slave core
NetTimeLogic’s NMEATime Of Day (ToD) Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to …
NMEA Time of Day (ToD) Master core
NetTimeLogic’s Time Of Day (ToD) Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to syn…
NetTimeLogic’s IRIG Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to an…
NetTimeLogic’s IRIG Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize othe…
Pulse Per Second Master (PPS) core
NetTimeLogic’s PPS Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other…
Pulse Per Second Slave (PPS) core
NetTimeLogic’s PPS Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a P…
Time aligned Signal Timestamper core
The Signal Timestamper from NetTimeLogic is a timestamper with nanosecond resolution (second and nanosecond format).
Time aligned Signal Generator core
The Signal Generator from NetTimeLogic is a clock aligned pulse and pattern (PWM) generator with nanosecond resolution (second an…
The Adjustable Clock from NetTimeLogic is an adjustable counter clock with nanosecond resolution (second and nanosecond format).
IEEE1588 & IEEE802.1AS PTP Timestamp Unit (TSU) core
NetTimeLogic’s PTP Timestamp Unit is an implementation of a single port Frame Timestamp Unit (TSU) according to IEEE1588-2008 (PT…
IEEE1588 & IEEE802.1AS PTP Hybrid Clock (HC) core
The PTP Hybrid Clock (HC) from NetTimeLogic is a combination of NetTimeLogic's PTP Transparent Clock (TC) and PTP Ordinary Clock …
IEEE1588 & IEEE802.1AS PTP Transparent Clock (TC) core
The PTP Transparent Clock (TC) from NetTimeLogic is a fully scalable implementation of a Peer-To-Peer, One-Step Transparent Clock…
IEEE1588 & IEEE802.1AS PTP Ordinary Clock (OC) core
The PTP Ordinary Clock (OC) from NetTimeLogic is an extension to a single port of NetTimeLogic's PTP Transparent Clock (TC).
Time Sensitive Networking (TSN) IIC(R) Plugfest Application core
The TSN Industrial Internet Consortium(R) (IIC) Plugfest Application is a companion core for the TSN IP cores from NetTimeLogic.