Avalon compliant I²C Master IP core provides an interface between Nios II processor and an I²C Slave device.
- I2C / I3C
- Now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Avalon compliant I²C Master IP core provides an interface between Nios II processor and an I²C Slave device.
The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
The M429GEN IP implements a synchronous single-chip ARINC 429 Transmit and Receive Controller capable of linking one CPU to one o…
AAC-LC and HE-AAC Audio Decoder
The AAC-LC and HE-AAC Audio Decoder (CWda73) is an audio IP core for decoding up to 6 audio channels in real-time.
AAC-LC and HE-AAC Audio Encoder
The AAC-LC and HE-AAC Audio Encoder (CWda72) is an audio IP core for encoding up to 6 audio channels in real-time.
20-bit -120dB THD+N Multi-Channel Audio Sample Rate Converter
The ASRC-premier (CWda54) is part of Coreworks family of multi-channel Asynchronous Audio Sample Rate Converter (ASRC).
16-bit -90dB THD+N Multi-Channel Audio Sample Rate Up Converter
The ASRC-lite-up (CWda53) is part of Coreworks family of multi-channel Audio Asynchronous Sample Rate Converters (ASRC).
Specifications: UAL_200 1.0 Interfaces: 802.3 dj compliant, UPLI DUT Types/Topology: Protocol TL Phy DL Reconciliation Sub Layer…
2.26GHz/2.46GHz Fractional-N LC Phase-Locked Loop with oscillator
180XFAB_PLL_01 uses 2.25792GHz/2.4576GHz Phase locked loop frequency synthesizer for clock generation.
1.22V/1uA Reference voltage and current source
180XFAB_RS_01 consists of a bandgap reference voltage regulator, formed temperature and power supply variations independent volta…
1-VIA’s ultra-high-speed and ultra-low-power PCIe Gen 3/4/5 SerDes technology is customizable to meet your requirements for a wid…
The CORDIC IP provides hardware acceleration of mathematical functions (mainly trigonometric ones) commonly used in motor control…
The Fast Fourier Transforms (FFT) are an efficient class of algorithms for digital computation of the Discrete Fourier Transform …
Cryptographic engine using the DES, Triple-DES or AES
The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES, AES or SM4 algorithms.
Security Hash, SM3 Hash and HMAC Engine
The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512), …
On-the-fly decryption engine FRTDEC allows to decrypt on-the-fly AXI traffic based on the read request address information.
Asymmetric cryptographic accelerator
The ACrypto Engine is an asymmetric cryptographic accelerator suitable for embedded application.
PCIe Controller is a high performance PCIE controller, it can support PCIE 1.0/2.0/3.0/4.0 protocol, and the support speed is 2.5…
XEC is a high performance 1000M/100M/10M Ethernet Controller IP.
The DDR PHY IP is a combination of hard macro, I/O Pad and synthesizable RTL to provide a physical interface to JEDEC standard DD…