M-JPEG Encoder (100 embedded quality levels)
This IP core has been developed to be a standards compliant High Speed M-JPEG Hardware Encoder.
- Video Processing
- Implemented into ASIC and FPGA projects
- Source code / Netlist
- ISO/IEC 10918-1 , ITU-T T.8…
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
M-JPEG Encoder (100 embedded quality levels)
This IP core has been developed to be a standards compliant High Speed M-JPEG Hardware Encoder.
Triple HD-video AFE digitizer - 10bits/170Mhz - 8bits/205Mhz
This macro is a triple-channel, 8/10-bits video analog front end (AFE) that incorporates all of the functions required to digitiz…
Crystal oscillator 10-30Mhz with digital frequency adjustment ± 100ppm
The V-Trans VT18DCXO crystal oscillator cell provides a low phase-noise output, with a low frequency variation over temperature.
Triple DAC 10-Bits, voltage output - 10Mhz, 3.3V/1.3V full-scale
This IP is a triple channel 10-bits 10 MS/s general purpose voltage output DAC, optimized for analog LCD controller application a…
Triple Video DAC 10-Bits, 240Mhz
This IP is composed of a triple channel 10-bits 240 MS/s DAC, designed for industry standard 0.18um 1P6M CMOS technology supplied…
100~450MHz DDR DLL with 80 Phase Selection, SMIC0.1.3um
The AR531S13 is a low-jitter low power dual channel delay locked loop (DLL) design support for DDR application.
40-450MHz Programmable Clock Generator PLL, SMIC0.13um
The AR530S13 is a low power programmable phase locked loop (PLL) featured with wide output frequency range from 50MHz to 450MHz.
TSMC CLN90LP 90nm DDR DLL - 164MHz-820MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN90GT 90nm DDR DLL - 335MHz-1675MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN90GOD 90nm DDR DLL - 272MHz-1360MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN90G 90nm DDR DLL - 196MHz-980MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN80HS 80nm DDR DLL - 316MHz-1580MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN80GT 80nm DDR DLL - 335MHz-1675MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN80GC 80nm DDR DLL - 196MHz-980MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN65LP 65nm DDR DLL - 164MHz-820MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN65GP 65nm DDR DLL - 316MHz-1580MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN55GP 55nm DDR DLL - 316MHz-1580MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN40LP 40nm DDR DLL - 84MHz-420MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN40LP 40nm DDR DLL - 112MHz-560MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN40LP 40nm DDR DLL - 177MHz-885MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…