UMC L130LL 130nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- UMC
- 130nm
- LL
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UMC L130LL 130nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
Bitmap 2.5D Graphics Accelerator
The logiBMP is 2.5D graphics accelerator from Xylon logicBRICKS IP library, optimized for Xilinx FPGAs and designed to speed up g…
Ultra Low-power, compact Hybrid Viterbi Decoder
This IP core is available with a configurable number of ACS units to suit a range of throughput requirements.
Band-gap Reference in GF N65 LP. Multiple voltages referenced to internal and external resistors.
The PMCC_REFS IP block combines two modules of GM current references and one module of BG (band-gap) current reference.
Color Camera Sensor Bayer Decoder
Today most common single-chip cameras use CMOS sensors with pixels arranged in Bayer color pattern.
VISENGI's JPEG Decoder IP core has been developed to be a standards compliant M-JPEG Hardware Decoder.
Fractional N PLL 8.5-11.3GHz in GF N65
PMCC_PLL12GFN is a macro-block designed for synthesizing the frequencies required for fiber optic transceivers and serdes using c…
Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain
PMCC_SERDES12G is a macro-block consisting of a 32:1 serializer and 1:32 deserializer with supporting functions such as CDR, CMU,…
Dual SATA Host controller on Virtex 5 FXT FPGA
The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
High-throughput Low-memory Viterbi Decoder
This IP core is available in either normal or high throughput configurations.
This implementation of the AES-CCM algorithm implements the full NIST draft SP800-38C specification.
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the inpu…
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC).
High-performance implementation of Z80/Z180 instruction set
Two clock cycle machine cycle implementation of the Z80/Z180 instruction set.
25 Gb/s AES-ECB 128/192/256 Crypto Cores
Concurrent EDA AES cores implement the 128-bit block size NIST FIPS AES Algorithm.
FPD-link, 30Bits Color LVDS Receiver, 150Mhz (SVGA/WXGA)
Now available up to 150Mhz (90Mhz previously) V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI speci…
Dual RSDS Transmitter, 24/18-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the t…
EA/MZ Modulator Driver 1.25Gb/s to 11.3Gb/s
The PMCC_EAMD12G is designed to directly drive the inputs of EA or MZ Modulators or EML devices at data-rates up-to 11.3Gbps.
Elliptic Curve Point Multiply and Verify Core
Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curve…
ADC 12-bit 80Mhz Dual channel - 3.3V
This dual channel Analog -to-Digital converter IP is based on a monolithic differential pipelined architecture with output error …