Low Power FracN/SSCG PLL on TSMC CLN6FF
The low power Fractional-N SSCG PLL addresses power sensitive designs required for IOT, mobile and other low power applications n…
- TSMC
- 6nm
- N6FF
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Low Power FracN/SSCG PLL on TSMC CLN6FF
The low power Fractional-N SSCG PLL addresses power sensitive designs required for IOT, mobile and other low power applications n…
Low Power Frac-N PLL on GLOBALFOUNDRIES 40LP
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.
Low Power Frac-N on TSMC CLN28HPC+
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.
Low Power Frac-N on TSMC CLN28HPC
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.
Low Power Frac-N on TSMC CLN22ULL
A programmable on-the-fly Fractional-N PLL is required to lock to an incoming clock source and produce an output clock.
Low Power Frac-N on TSMC CLN16FFC
The low power Fractional-N PLL addresses power sensitive designs required for IOT, mobile and other low power applications needin…
Low Power Frac-N on TSMC CLN12FFC
The low power Fractional-N PLL addresses power sensitive designs required for IOT, mobile and other low power applications needin…
Low Power Cascade PLL on TSMC CLN65LP
The low power cascade PLL addresses a large portfolio of applications, ranging from non-integer clock multiplication to programma…
Low Power 32KHz Crystal Oscillator on TSMC CLN16FFC
High end consumer and professional applications require crystals with a minimum number of external components.
Low Power 32KHz Crystal Oscillator on TSMC CLN12FFC
High end consumer and professional applications require crystals with a minimum number of external components.
Low Power 1-22G PCIe Gen4 / SAS4 PHY on TSMC CLN16FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS) capable…
Low Noise Crystal Oscillator on TSMC CLN7FF
High end consumer and professional applications require crystals with a minimum number of external components.
Low Noise Crystal Oscillator on TSMC CLN6FF
High end consumer and professional applications require crystals with a minimum number of external components.
Low Noise Crystal Oscillator on TSMC CLN5
High end consumer and professional applications require crystals with a minimum number of external components.
The Low Jitter PLL creates a high quality clock with good duty cycle and jitter characteristics useful for source synchronous int…
LDO for CPU Cores on TSMC CLN3P-CLN3X
The Scalable LDO (Low Drop Out) Regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully …
LDO for CPU Cores on TSMC CLN3E
The Scalable LDO (Low Drop Out) Regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully …
LDO for CPU Cores on TSMC CLN2P
The Scalable LDO (Low Drop Out) Regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully …
Jitter Cleaning PLL on TSMC CLN40G
The Jitter Cleaning PLL macro is implemented in Analog Bits’ proprietary architecture that uses 0.9V core and 1.8V IO oxide devic…
Integrated Bandgap and Current Reference on TSMC CLN7FF
The Integrated Bandgap and Programmable Current Reference macro comprehensively addresses typical SOC voltage and current referen…