The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
- PHY
- TSMC
- 65nm
- GP
- Available on request
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
Multi-Channel HDTV H.264/AVC Limited Baseline Video Decoder
The OL_H264MCLD core is a hardware implementation of the H.264 baseline video compression algorithm.
The GRPCI2 IP core provides a 32-bit master/target interface for AMBA AHB-2.0 systems.
Bit Block Transfer 2D video accelerator
The logiBITBLT is 2D graphic accelerator or BitBlitter IP core from Xylon logicBRICKS™ IP library.
Compact Multilayer Video Controller
The logiCVC-ML IP core is an display graphics controller that enables an easy video and graphics integration into embedded system…
The LEON3 processor offers robust fault tolerance and performance for space and high-reliability applications, including satellit…
10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface
The GRETH_GBIT core implements a 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface.
HDTV H.264/AVC Limited Baseline Video Decoder
The OL_H264LD core is a hardware implementation of the H.264 baseline video compression algorithm.
Avalon Multi-port SDRAM Memory Controller IP Core
The Microtronix Avalon Multi-port SDRAM Memory Controller IP Core is designed for maximizing the performance of an Altera Nios II…
IEEE 802.15.4 (ZigBee) CCM* AES Cores
IEEE 802.15.4 is the low-power wireless standard that is used by ZigBee Alliance as a base of its ZigBee™ specification.
Implementation of the new encrypted shared storage media standard IEEE P1619 with AES cipher in the LRW mode.
Intel 8255A Functional Equivalent Programmable Peripheral Interface
The DB8255A Programmable Peripheral Interface core is a full function equivalent to the Intel 8255A / 82C55A and Intersil 82C55A …
Intel 8279 Functional Equivalent Programmable Keyboard/Display Interface
The DB8279 Programmable Keyboard / Display Interface core is a full function equivalent to the Intel 8279 / Mitsubishi 8279 / NEC…
Combo P1619 / 802.1ae (MACSec) GCM-AES/LRW-AES Cores
LAN security standard IEEE 802.1ae (MACSec) uses AES cipher in the GCM mode, while the disk/tape encryption standard IEEE P1619 u…
Deeply embedded processor for deterministic real-time applications
The Cortex-R4 processor delivers high-performance, real-time responsiveness, reliability, and dependability with high error-resis…
P1619/802.1ae (MACSec) GCM/XEX/XTS-AES Core
General Description LAN security standard IEEE 802.1ae (MACSec) uses AES cipher in the GCM mode, while the disk/tape encryption s…
The NTadpcm core is fully compliant with G.726 standard and supports up to 64 full duplex voice channels.
Clock and Data Recovery of HDB3/B3ZS coded signals
An all-digital solution suitable for clock/data recovery of HDB3/B3ZS coded signals.
Additive White Gaussian Noise Generator
A configurable AWGN generator that can be used as emulator of a noisy transmission channel.
Configurable interleaving/deinterleaving function that can be used in a wide range of applications that employ channel coding.