PCI Bridge
The GRPCI2 IP core provides a 32-bit master/target interface for AMBA AHB-2.0 systems.
Overview
The GRPCI2 IP core provides a 32-bit master/target interface for AMBA AHB-2.0 systems. It includes parameterizable FIFOs for both master and target operation, and can optionally be provided with an independent DMA engine.
Key features
- 2-bit PCI interface
- PCI bus master and target
- AMBA AHB/APB 2.0 back-end interface
- Configurable FIFOs for both master and target operation
- Supports incremental bursts and single accesses
- Bus master capabilities
- Memory read, memory write
- Memory read multiple
- Memory read line
- I/O read, I/O write
- Type 0 and 1 configuration read and write
- Host bridging
- Target capabilities
- Type 0 configuration space header
- Configuration read and write
- Parity generation (PAR)
- 2 Memory BARs
- Memory read, memory write
- Memory read multiple
- Memory read line
- Memory write and invalidate
- Optional DMA engine add on
- Software support for GRPCI hosts in Linux 2.6, RTEMS and VxWorks
Benefits
- Available in GPL for evaluation
- Low cost commercial license
- Easily integrated through AMBA plug&play
- Low-area overhead
What’s Included?
- Fully synthesisable VHDL code
- VHDL test bench
- Ducumentation
- Optional FPGA evaluation board
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Protocol Bridge IP cores
What is PCI Bridge?
PCI Bridge is a Protocol Bridge IP core from Frontgrade Gaisler listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.