Vendor: Noesis Technologies Category: Data Compression

ADPCM G.726 Codec

The NTadpcm core is fully compliant with G.726 standard and supports up to 64 full duplex voice channels.

TSMC 180nm BCDG2 Silicon Proven View all specifications

Overview

The NTadpcm core is fully compliant with G.726 standard and supports up to 64 full duplex voice channels. The core is used in applications that require reduction in transport and storage bandwidth requirements. It significantly offloads CPU tasks as a co-processing system element.

Key features

  • Compliant with ITU G.721, G.723, G.726 and G.726-Annex recommendations.
  • On-the-fly configuration for variable compression rate, PCM law.
  • Process capability of up to 64 full duplex or up to 128 half duplex voice channels.
  • Burst and continuous mode support.
  • No register based configuration is required.
  • A-law, u-law linear code format selection.
  • Fully compliant to ITU test vectors (ITU G.726-A2).

Block Diagram

ntADPCM block diagram

What’s Included?

  • Synthesizable VHDL or Verilog code.
  • C++ model for system simulation.
  • Comprehensive test bench.
  • Detailed user's guide.

Silicon Options

Foundry Node Process Maturity
TSMC 180nm BCDG2 Silicon Proven

Specifications

Identity

Part Number
ntADPCM
Vendor
Noesis Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Noesis Technologies
HQ: Greece

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Frequently asked questions about Data Compression IP

What is ADPCM G.726 Codec?

ADPCM G.726 Codec is a Data Compression IP core from Noesis Technologies listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Data Compression?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Data Compression IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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