TSMC CLN28HPC 28nm Deskew PLL - 350MHz-1750MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 28nm
- HPC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
TSMC CLN28HPC 28nm Deskew PLL - 350MHz-1750MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CLN28HPC 28nm Deskew PLL - 700MHz-3500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CLN28HPC 28nm DDR DLL - 150MHz-750MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN28HPC 28nm DDR DLL - 200MHz-1000MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN28HPC 28nm DDR DLL - 316MHz-1580MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN28HPC 28nm Clock Generator PLL - 175MHz-875MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPC 28nm Clock Generator PLL - 350MHz-1750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPC 28nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
Common Public Radio Interface (CPRI) v.6.1 IPC
CPRI (Common Public Radio Interface) is an interfacing standard for high-speed communication of digital radio samples and control…
JPEG Encoder 8K(YUV422) 48fps@200MHz. (16Sample/clk)
The KJN-8EX_ENC consists of IP cores that conform to the JPEG Extended DCT-based process for compressing 8bit/12bit still images.
TCP/IP Offload Engine - 10G/ 25G/40G/100Gbit/s TCP/IP
Fast, reliable connectivity in any FPGA using a minimum of FPGA resources The TCP/IP (Transmission Control Protocol/ Internet Pro…
The Ceva-Waves Wi-Fi platforms portfolio provide a comprehensive selection of hardware IP and CPU-agnostic host software for ener…
Mobiveil’s Enterprise Flash Controller (EFC) is a flexible and configurable design targeted for enterprise storage applications l…
The nSAD_TS180_1V8_AD14b2M is a 14b 2MS/s, 13 ENOB, low-power SAR fully-differential AD converter designed on the TSMC 180 proces…
JPEG Encoder 8K(YUV422) 96fps@200MHz. (32Sample/clk)
The KJN-9EX_ENC consists of IP cores that conform to the JPEG Extended DCT-based process for compressing 8bit/12bit still images.
The Microtronix Camera Link Aligner IP Core is designed for building Frame Grabber (Receiver) Medium & Full Channel Link™ interfa…
JPEG-LS Lossless Image Encoder
The Lancero JPEG-LS Lossless Image Encoder IP Core is a efficient FPGA based implementation of the ITU T.87 lossless image compre…
Reconfigurable Parallel CRC Generator
Parallel CRC IP is reconfigurable high-speed CRC generator, flexible in terms of input data width and generating polynomial.
JPEG Decoder 8K(YUV422) 48fps@200MHz, (16Sample/clk)
The KJN-8EX_DEC conform to the JPEG Extended DCT-based process for decompressing 8bit/12bit still images.
The DVB-T2 core allows the transmission of an MPEG-TS data stream to a digital to analog converter in base band, IF or RF mode.