Leveraging the benefits of USB 3.2 Gen 1 device controller, USB 3.2 Gen 2 is designed using the FPGA built-in transceiver.
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Leveraging the benefits of USB 3.2 Gen 1 device controller, USB 3.2 Gen 2 is designed using the FPGA built-in transceiver.
This IP core implements the Kuznyechik cipher of the Russian Federation GOST 3412-2015 standard (also available in English as RFC…
Ultra-low power and high performance 12bit 1Msps SARADC
Supports 1Ksps~2Msps sampling rate; 8-channel differential inputs or 20-channel single-ended inputs; High performance: ENOB>=11.0…
Ultra-low power and high performance 12bit SARADC (2.7V~3.6V)
Supports 1Ksps~4Msps sampling rate; 4-channel differential inputs or 8-channel single-ended inputs; High performance: ENOB>=11.0b…
5.0V/3.3V-->3.3V/1.5V capacitor-free regulator
Supports capacitor-less application with fast transient; Typical output 1.50V, output range is from 1.40V to 1.65V; 200mA driving…
DVB S2/S Satellite Tuner SoC White Box IP
This satellite tuner is a direct-conversion (zero IF) receiver for digital TV Broadcasting.
XRX015LGCLFLASH_16K16 is a logic compatible embedded non-volatile memory IP with 16K16 ROM density.
XRX013HVPLFLASH_3K128 is a HV compatible embedded non-volatile memory IP with 3K128 ROM density.
XRX013HVPLFLASH_2K128 is a HV compatible embedded non-volatile memory IP with 2K128 ROM density.
XRX011LGCLFLASH_4K32 is a logic compatible embedded non-volatile memory IP with 4K32 ROM density.
USB 2.0 Device Controller with ULPI interface
The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver.
Scalable RSA and Elliptic Curve Accelerator
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponen…
14-bit, 50 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B50M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process with an optional input buf…
JPEG Decoder Full HD(YUV422) 30fps@63MHz. (2Sample/clk)
The KJN-F4DEC conform to the JPEG baseline format for decompressing still images.
JPEG Encoder Full HD(YUV422) 30fps@63MHz. (2Sample/clk)
The KJN-F4ENC conform to the JPEG baseline format for compressingstill images.
JPEG Codec Full HD(YUV422) 30fps@63MHz. (2Sample/clk)
The KJN-F4 conform to the JPEG baseline format for compressing/decompressing still images.
The so_ip_sata3_hctrl is a soft core implementation of SATA host controller as defined in the SATA Specification 3.2.
Up to 1,500 MIPS @ 200 Mhz clock frequency for high data processing speed and precise process control The Generic Timer IP module…
Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter
CorePLL is a wideband phase-locked loop (PLL) system for 2G (GSM) 3G and 4G (LTE), including Carrier Aggregation (CA) for 3GPP Re…
10-bit 1-channel 2.6 kSPS SAR ADC
IP 250iHP_ADC_09 is 10-bit 2.6 kSPS ADC employs high-performance single ended successive approximation architecture with embedded…