Xilinx, Inc.
•
HQ:
USA
Remote Debug using Vivado Design Suite Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and prov…
- Debug Trace
Compare 908 xilinx/ IP Listing from 116 vendors
-
-
25 Gb/s AES-ECB 128/192/256 Crypto Cores
Concurrent EDA, LLC• HQ: USAConcurrent EDA AES cores implement the 128-bit block size NIST FIPS AES Algorithm.
- Symmetric Crypto
- Mature
- Now
- Implements AES to NIST FIPS…
-
Xilinx, Inc.• HQ: USA
The Xilinx® LogiCORE™ IP HMC Controller implements a high performance, configurable HMC host controller for user to interconnect …
- HBM
-
Xilinx MicroBlaze Trace Core (XMTC)
Xilinx, Inc.• HQ: USAThis document provides the design specification for the Xilinx MicroBlaze Trace Core (XMTC), which provides instruction and data …
- Debug Trace
-
Xilinx Ultra Scale Plus SATA HOST IP
Logic Design Solutions• HQ: FRANCEThe LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4…
- SATA Controller
- Good
- Now
- SATA 3
-
Helion Technology Limited• HQ: UK
The Helion ARC4 core implements the Alleged RC4 stream cipher algorithm.
- Symmetric Crypto
- now
-
Hardware Security Module (HSM) for AMD Xilinx Versal ACAP device
Secure-IC• HQ: FranceThe HSM IP module is a Hardware Security Module for a wide range of applications.
- Root Of Trust
-
Hardware Security Module (HSM) for Xilinx Zynq UltraScale+ MPSoC platform
Secure-IC• HQ: FranceThe HSM IP module is a Hardware Security Module for a wide range of applications.
- Root Of Trust
-
Deep capture / high visibility Debug IP for Xilinx FPGA
Exostiv Labs• HQ: BelgiumThe customizable EXOSTIV IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design with…
- Debug Trace
- Now
-
SATA Host on Xilinx Zynq Artix 7
Logic Design Solutions• HQ: FRANCEThe LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 F…
- SATA Controller
- Good
- Now
- SATA II
-
SATA 3 Host Controller on Xilinx Artix 7
Logic Design Solutions• HQ: FRANCEThe LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 F…
- SATA Controller
- Good
- Now
- SATA 3
-
Xilinx UltraScale Plus NVME Hhost IP
Logic Design Solutions• HQ: FRANCEThe LDS NVME HOST ZUP IP is one of the most flexible NVME HOST IP in the market.
- NVMe Controller
- Good
- Now
- NVME 1.3
-
Xilinx Ultra Scale NVME Host IP
Logic Design Solutions• HQ: FRANCEThe LDS NVME HOST K7U IP is one of the most flexible NVME HOST IP in the market.
- NVMe Controller
- Good
- Now
- NVM Express
-
Extensible Framework (EFW) For Xilinx KC705 Module
Hitek Systems LLC• HQ: USAExtensible FPGA Framework (EFW) provides a verified set of productivity solutions, including module targeted physical interface c…
- System Controller
- Stable, Hardware verified
- Available Now
-
Xilinx, Inc.• HQ: USA
The Xilinx LogiCORE™ IP Gamma LUT core provides an optimized hardware block for manipulating image data to match response of disp…
- Image Conversion
-
Xilinx, Inc.• HQ: USA
The Xilinx LogiCORE™ IP Sensor Demosaic core provides an optimized hardware block that reconstructs sub-sampled color data called…
- Image Conversion
-
MicroBlaze Microcontroller Reference Design
Xilinx, Inc.• HQ: USAMicroBlaze™ is a 32-bit RISC soft processor core that can be used with soft peripherals to design embedded systems in Xilinx FPGA…
- MCU
-
Xilinx, Inc.• HQ: USA
The Xilinx® LogiCORE™ IP Debug Bridge core is a controller which provides a mechanism to establish a communication channel for de…
- Protocol Bridge
-
7 Series Integrated Block for PCI Express (PCIe)
Xilinx, Inc.• HQ: USAXilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and inc…
- PCI Express
-
64-bit Initiator/Target for PCI-X & 32- and 64-bit Initiator/Target for PCI
Xilinx, Inc.• HQ: USADO-DI-PCIX64-VE rolls the Initiator/Target for PCI ™/PCI-X ™, 32-bit Initiator/Target for PCI and 64-bit Initiator/Target for PCI…
- PCI