PCI-Express IP Listing

The Renesas PCIe 4.0 Dual Mode Link Controller IP is compliant with the "PCI Express (PCIe) 4.0 Base Specification".

• PCI Express

The High Channel Count (HCC) DMA IP core for PCI-Express is a PCIe Endpoint with multiple industry standard AXI Interfaces.

• PCI Express

LeWiz makes available its low-latency PCI-express framework for IP licensing - targeting low-latency applications such as those i…

• PCI Express

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…

• TSMC
• 28nm
• HPC

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…

• TSMC
• 40nm
• G

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…

• TSMC
• 28nm
• HPL

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…

• TSMC
• 40nm
• G

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…

• Samsung
• 8nm
• 8LPP

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…

• GlobalFoundries
• 65nm
• G

Compliant to PCI Express base specification 5.0

• PCI Express

SD Express Verification IP is an solution in the market for the verification of SD Express implementations.

• Verification IP

The AXI Bridge for PCIe IP core is the IP solution with a mix of multiple industry standard memory mapped AXI Interfaces.The AXI …

• Protocol Bridge

The Multi-Channel AXI DMA engine IP Core for AXI4 is a programmable AXI Stream to AXI memory mapped bridge with sophisticated dat…

• DMA

The AXI Bridge with DMA IP core is the ultimate PCIe DMA IP solution with a mix of multiple industry standard AXI Interfaces.

• Protocol Bridge

The silicon-proven Gigabit Ethernet IP core provides a 10/100 Mbps Media Independent Interface (MII) and a 1000 Mbps Gigabit Medi…

• Ethernet

The Fast Ethernet Media Access Controller (FEMAC) with AHB or AXI Interface core incorporates the essential protocol requirements…

• Ethernet

The 10/100 Ethernet Media Access Controller (MAC) IP core is compliant with the Ethernet IEEE 802.3-2002 standard and has passed …

• Ethernet

The Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard and supports protocol ext…

• Ethernet

The 10 Gigabit Ethernet (XGMAC) IP core is compliant with the Ethernet IEEE 802.3-2008 standard and provides an interface between…

• Ethernet

The Differential IO Buffer macros provide a low noise, high performance differential output clock that is compatible with HCSL (H…

• TSMC
• 7nm
• N7FF