What is Video Interlacer?
Video Interlacer is a Video Processing IP core from Zipcores Electronic Systems Engineering S.L. listed on Semi IP Hub.
The INTERLACER IP Core is a fully pipelined video interlacer solution that converts any progressive video format into its interla…
The INTERLACER IP Core is a fully pipelined video interlacer solution that converts any progressive video format into its interlaced equivalent. The format of the input video is defined by the parameters pixels_per_line and lines_per_frame. These values specify the size of one input frame of video in pixels and lines. Each interlaced output field will have half the number of lines as an input frame.
The input and output interfaces are streaming interfaces that follow a simple valid-ready pipeline protocol1. Input pixels and syncs are sampled on the rising edge of clk when pixin_val and pixin_rdy are both high. Likewise, output pixels and syncs are sampled on the rising edge of clk when pixout_val and pixout_rdy are high. The interfaces are compatible with all Zipcores video IP Cores and allow for easy connectivity between modules.
The input sync signals vsync and hsync are sideband flags that are coincident with the first pixel of a frame and the first pixel of a line respectively. The output sync signals are coincident with the first pixel of an output field. Note that the output interface has an additional field flag that identifies whether the field is odd or even. This field flag is held high or low for the duration of the output field.
Note that if no flow control is required in the design and the output is guaranteed to accept pixels without stalling, then the signal pixout_rdy may be tied high and the signal pixin_rdy may be ignored.
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Video Interlacer is a Video Processing IP core from Zipcores Electronic Systems Engineering S.L. listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.
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