Integer-N PLL, 32M ~ 256MHz on UMC 55nm
UniIC
•
HQ:
China
This present IP is a Phase Locked Loop (PLL) circuit.
- UMC
- 55nm
Compare 36 UniIC IP Cores from 1 vendors
-
-
Integer-N PLL, 800M-3.2G on TSMC 12nm
UniIC• HQ: ChinaThis present IP is a charge-pump Phase Locked Loop (PLL) circuit, which can cover 800MHz-3200MHz vco output frequency.
- TSMC
- 12nm
- FFC
- Silicon Proven
-
Comparator with configurable hysteresis input on UMC 55nm
UniIC• HQ: ChinaThis present IP is a comparator which is used to do the comparison between the different input groups, which operates in 3.3v pow…
- UMC
- 55nm
- Silicon Proven
-
Charge-Pump positive voltage generator with LDO in-built on SMIC 65nm
UniIC• HQ: ChinaThe present IP is a charge-pump and low dropout voltage generator, which is developed with SMIC 65nm ETOX Nor Flash process.
- SMIC
- 65nm
- LL
- Silicon Proven
-
The present IP is a charge-pump voltage generator developed using SMIC's 65nm ETOX Nor Flash process.
- SMIC
- 65nm
- LL
- Silicon Proven
-
The present IP is a charge-pump voltage generator developed using SMIC's 65nm ETOX Nor Flash process.
- SMIC
- 65nm
- LL
- Silicon Proven
-
Low Power BandGap Reference with chopper on SMIC 40nm
UniIC• HQ: ChinaThe IP is a Band-gap reference generator circuit.
- SMIC
- 40nm
- Silicon Proven
-
Low Power BandGap Reference on SMIC 65nm
UniIC• HQ: ChinaThe BGR IP is a BandGap reference circuit for low-power application which just consumes 3.2uA in operation which works well in 1.…
- SMIC
- 65nm
- LL
- Silicon Proven
-
Low Power BandGap Reference on SMIC 40nm
UniIC• HQ: ChinaThe BGR IP is a BangGap Reference for low-power application.
- SMIC
- 40nm
- Silicon Proven
-
PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm
UniIC• HQ: ChinaThe PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device.
- TSMC
- 22nm
- ULL
-
DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
UniIC• HQ: ChinaThe DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device.
- TSMC
- 12nm
- FFC
-
DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm
UniIC• HQ: ChinaThe DDR4&LPDDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM devi…
- TSMC
- 22nm
- ULL
-
UniIC• HQ: China
MIPI RX PHY is a mass production IP for D-PHY v1.2 and C-PHY v1.2 protocols.
- MIPI PHY
- Mass Production
-
MIPI RX controller on SMIC 28nm
UniIC• HQ: ChinaMIPI RX controller is a mass production IP in SMIC 28nm supported MIPI DSI & DCS protocols.
- MIPI
- Mass Production
-
UniIC• HQ: China
DSC decoder IP is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a.
- VESA DSC
- Mass Production
-
Temperature Sensor with PTAT voltage output on XMX 55nm
UniIC• HQ: ChinaThe present IP is Temperature sensor (TS) circuit.
- Temperature Sensor