Faraday Technology IP Cores

UMC 55nm SP Low-K Logic process synchronous Two Port Register File memory compiler.

• UMC
• 55nm
• SP

UMC 55nm SP/RVT and HVT Low-K Logic process synchronous ultra high density/6T cell Two Port Register File memory compiler.

• UMC
• 55nm
• SP

UMC 0.11um LL/AE (AL Enhancement) Logic process synchronous high density Two Port Register File SRAM memory compiler.

• UMC
• 110nm
• LL

UMC 90nm Logic process low leakage devices synchronous Low Power Single Port hihg density memory compiler.

• UMC
• 90nm
• LL

UMC 90nm LL/RVT Low-K Logic process Synchronous high density Single Port SRAM compiler With Redundancy.

• UMC
• 90nm
• LL

UMC 90nm SP/RVT Low-K Logic process Single Port SRAM (Introduce Redundancy feature to the existing FSD0A_B_SH).

• UMC
• 90nm
• SP

UMC 90nm SP/ Low-K Logic process Synchronous high density Single Port SRAM compiler With Redundancy.

• UMC
• 90nm
• SP

UMC 65nm LL/RVT Low-K Logic process synchronous Single Port SRAM.

• UMC
• 65nm
• LL

UMC 65nm LL/RVT Low-K Logic process 1-port high density memory compiler.

• UMC
• 65nm
• LL

UMC 65nm LL/RVT Low-K process synchronous high density, Single Port SRAM compiler with the row redundancy.

• UMC
• 65nm
• LL

UMC 65nm SP Low-K Logic process synchronous high density Single Port SRAM with redundaycy memory compiler.

• UMC
• 65nm

UMC 65nm SP Low-K Logic process synchronous high density Single Port SRAM memory compiler.

• UMC
• 65nm

UMC 55nm SP Low_K Logic process synchronous high density One Port Register File compiler.

• UMC
• 55nm
• SP

UMC 55nm SP Low_K Logic process synchronous high density Single Port SRAM memory compiler with row-pair redundancy.

• UMC
• 55nm
• SP

UMC 55nm SP Low_K Logic process synchronous high density Single Port SRAM memory compiler.

• UMC
• 55nm
• SP

UMC 55nm SP Low-K Logic process synchronous ultra high speed Single Port SRAM memory compiler.

• UMC
• 55nm
• SP

UMC 55nm SP/RVT+HVT Low-K Logic process synchronous high density Single Port SRAM memory compiler.

• UMC
• 55nm
• SP

UMC 55nm SP/RVT Low-K Logic process synchronous Low Power (PG-DC) using 0.425-Bit cell Single Port Register File memory compiler.

• UMC
• 55nm
• SP

UMC 55nm SP/RVT Low-K Logic process synchronous Low Power (PG-DC) using 0.425-Bit cell Single Port SRAM memory compiler.

• UMC
• 55nm
• SP

UMC 55nm SP Low-K Logic process Low Power synchronous high density One Port Register File compiler.

• UMC
• 55nm
• SP