Faraday Technology IP Cores

Power on reset(POR) block, UMC 0.11um e-flash process.

• UMC
• 110nm

Vrr=2.2V Vfr=2.0V, B type IO, input VCCK=1.2V VCC3IO=3.3V, 3.3V Power On Reset, UMC 0.11um HS/AE (AL Enhancement) Logic process.

• UMC
• 110nm
• HS

Vrr=2.2V, Vfr=2.0V, A type IO, 3.3V Power On Reset, UMC 0.11um AL eFlash process.

• UMC
• 110nm

Power on Reset circuit tolerant with 0.25um, 2.5V MMC and Logic process VCC=2.5V, B type IO, Power On Reset, UMC 0.25um Logic pro…

• UMC
• 250nm

Vrr=1.8V Vfr=1.6V, VCC=2.5V, Ivcc=13.4uA, B type IO, Power On Reset, UMC 0.25um Logic process.

• UMC
• 250nm

Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA, Core type, Power On Reset, UMC 0.18um GII Logic process.

• UMC
• 180nm
• G

Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA, D type IO, Power On Reset, UMC 0.18um GII Logic process.

• UMC
• 180nm
• G

Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA, C type IO, Power On Reset, UMC 0.18um GII Logic process.

• UMC
• 180nm
• G

Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA, B type IO, Power On Reset, UMC 0.18um GII Logic process.

• UMC
• 180nm
• G

Vrr=0.8V, Vfr=0.65V, input VCC=1.2V, 1.2V Power On Reset, UMC 55nm 2T LP/RVT Low-K Logic process.

• UMC
• 55nm
• LP

Vrr=Vfr=0.8V, input VCC=1.2V, 1.2V Power On Reset, UMC 55nm 2T LP/RVT Low-K Logic process.

• UMC
• 55nm
• LP

Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=10.7uA, Core type, Power On Reset, UMC 0.13um LL Logic(FSG) process.

• UMC
• 130nm
• LL

Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=12.7uA, HS process with B-type IO., Power On Reset, UMC 0.13um HS/FSG Logic process.

• UMC
• 130nm
• HS

Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=12.7uA, HS process with A-type IO., Power On Reset, UMC 0.13um HS/FSG Logic process.

• UMC
• 130nm
• HS

Vrr=0.8V, Vfr=0.65V, input VCC=1.1V, 1.1V Power On Reset, UMC 40nm LP/RVT Low-K Logic process.

• UMC
• 40nm
• LP

Vrr=0.67V Vfr=0.63V, input 1.0V, Core type, Power On Reset (with Self-Test Circuit), UMC 90nm SP/RVT Logic Low-K process.

• UMC
• 90nm
• SP

Input clock:8MHz, output clock range:720 ~ 1680MHz wide-range SSCG, UMC 40nm LP process.

• UMC
• 40nm
• LP

Input clock range:5 ~ 1280MHz, output clock range:15.625 ~ 2000MHz wide-range SSCG, UMC UMC 40nm LP/LVT Low-K Logic process.

• UMC
• 40nm
• LP

Input 20M-135MHz, output 20M-135MHz SSCG, UMC 0.18um Logic process.

• UMC
• 55nm
• LP

Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.

• UMC
• 90nm
• SP