Faraday Technology IP Cores

1.1V Analog ESD IO cells with low capacitor for UMC 40nm LP process.

• UMC
• 40nm
• LP

UMC 28nm HLP Logic process, 3.3V Analog ESD IO Cell Library.

• UMC
• 28nm
• HLP

UMC 90nm SP/RVT Low-K Logic process high density Single Port 6T SRAM Memory Complier.

• UMC
• 90nm
• SP

UMC 90nm SP/RVT/ Low-K process synchronous ultra high speed SRAM compiler.

• UMC
• 90nm
• SP

UMC 90nm Logic process SP/ Low-K synchronous high density Single Port SRAM memory compiler.

• UMC
• 90nm
• SP

UMC 55nm eFlash with peripheral HVT & redundancy Single Port SRAM.

• UMC
• 55nm
• SP

UMC 55um LP Low-K process Singal-Port SRAM compiler with redundancy feature.

• UMC
• 55nm
• LP

UMC 55um LP Low-K process ULL Singal-Port SRAM compiler.

• UMC
• 55nm
• LP

UMC 55nm eFlash Single Port SRAM with row redundancy/HVT/Power Gating.

• UMC
• 55nm

UMC 55nm eFlash Single Port SRAM compiler with Power Gating /HVT.

• UMC
• 55nm

ULL Single Port SRAM with row redundancy, UMC 40nm LP process.

• UMC
• 40nm
• LP

UMC 40nm LP/LVT Single Port SRAM compiler with Power Gating & row redundancy.

• UMC
• 40nm
• LP

UMC 40nm LP/LVT Single Port SRAM compiler with peripheral LVT and Power Gating.

• UMC
• 40nm
• LP

ULL Single Port SRAM, UMC 40nm LP process.

• UMC
• 40nm
• LP

UMC 28nm HLP process synchronous high density Single Port SRAM memory compiler.

• UMC
• 28nm
• HLP

UMC 28nm HLP synchronous high density Single Port SRAM memory compiler.

• UMC
• 28nm
• HLP

UMC 28nm HLP process LVT synchronous high density Single Port SRAM memory compiler.

• UMC
• 28nm
• HLP

UMC 28nm HLP Logic process LVT synchronous high density Single Port SRAM memory compiler.

• UMC
• 28nm
• HLP

UMC 28nm HLP process standard LVT synchronous high density Single Port SRAM memory compiler.

• UMC
• 28nm
• HLP

UMC 28nm HLP Logic process LVT synchronous high density Single Port SRAM memory compiler.

• UMC
• 28nm
• HLP