We provide our clients with effective solutions to problems involving interconnection networks and reconfigurable computing. Our practice employs scalable, rule-based methods to tackle complex concurrency among heterogeneous processors.
Advances in chip technology and throughput of low cost computing platforms offer significant opportunities to radically improve performance of current products.
Atomic Rules understands the limitations of composing complex processor interactions using conventional RTL methods. To address this challenge, we use tools and techniques inspired by functional programming.
Beyond RTLs, we specialize in creating source codes written in Bluespec SystemVerilog, a vehicle for code correctness, portability and reuse. Atomic Rules provides its clients with expert SoC/FPGA competencies that build upon RTL/ESL design and verification techniques; not reinvent them.
Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component
Atomic Rules TimeServo is a RTL IP core that serves the function of an FPGA’s System Timer or Clock.
DPDK-aware FPGA/GPP data mover
Arkville provides a high-throughput line-rate agnostic conduit between FPGA hardware and GPP software.
Atomic Rules UDP Offload Engine (UOE) is a UDP FPGA IP Core that allows for immediate operation at 10, 25, 40, 50, 100 or 400 GbE.
Line-Rate UDP/IPv6 Offload for Modern FPGA Designs UOE6 is Atomic Rules’ next-generation UDP Offload Engine, purpose-built for IP…