USB 2.0 Device IP Core
A USB 2.0 Device IP Core that provides high performance small footprint solution for quick and easy implementation of a USB Devic…
Overview
A USB 2.0 Device IP Core that provides high performance small footprint solution for quick and easy implementation of a USB Device interface.
An USB 2.0 Device IP Core is ideal for applications where the target device must act as aperipheral only. It provides portable devices with a cost-effective way of conducting point-to-point communications using the USB bus.
ARCHITECTURE
The USB 2.0 Device IP Core supports both High Speed and Full Speed operations. It will automatically perform the required negotiation to determine if it's counter part supports High Speed and fall back to Full Speed operation if it does not. The speed negotiation is supported in device and host modes.
UTMI+ L2 PHY Interface
The USB 2.0 Device IP Core features an industry standard UTMI+ L2 interface. Any of-the-shelf UTMI+ L2 compliant PHY or PHY IP can be used with this IP Core.
ULPI Interface
An optional ULPI interface is provided for interface to a ULPI compliant PHY. The ULPI interface option reduces the typical pin count of UTMI+ L2 from over 30 to just 12 interface signals.
MCU Interfaces
The USB2.0Device IP Core features two WISHBONE interfaces:
The Slave Interface is used to access all core internal registers.
The Master Interface allows the USB 2.0 Device IP Core to share the system memory for buffering data. It is also used to store Transfer Descriptors when operating in Host Mode.
Buffer Memory
The USB 2.0 Device IP Core does not need dedicated buffer memory. It's WISHONE Master Interface and the internal DMA engine allow it to share the SoC's main memory for its buffers. Optionally we can also provide a WISHBONE bridge to attach standard dedicated SRAM.
Key features
- USB 2.0 high performance operation
- UTMI+ L2 Interface, ULPI wrapper and FS only transceiver interface available
- Full USB peripheral support
- High Speed and Full Speed mode support
- Up to 16 endpoints
- Bulk, interrupt and isochronous transfers
- Slave and Master System Interface:
- AHB
- AVALON
- OCP
- PLB
- OPB
- WISHBONE
- Customer specified bus interface
- No dedicated local memory required
- Compact and cost-effective solution for SoC
Block Diagram
Benefits
- Flexible
- Compact
- Cost-effective
What’s Included?
- Verilog Source Code
- Test Bench
- Sample Syntheis scripts
- Dcumentation
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about USB IP core
The Ubiquitous USB 2.0: Exploring Its Benefits and Widespread Adoption
Exploring USB Applications and the Impact of USB IP
Understanding USB IP and Its Role in SOC Integration
What Designers Need to Know About USB Low-Power States
New USB 80Gbps Specification Boosts Data Rate, Enables Four Protocols on One Bus
Frequently asked questions about USB IP cores
What is USB 2.0 Device IP Core?
USB 2.0 Device IP Core is a USB IP core from ASICS World Services, LTD. listed on Semi IP Hub.
How should engineers evaluate this USB?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.