Vendor: Faraday Technology Category: SRAM

UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT

UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT

Overview

UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT

Silicon Options

Foundry Node Process Maturity
UMC 40nm LP

Specifications

Identity

Part Number
FSH0L_D_SHHVT
Vendor
Faraday Technology
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about SRAM IP core

A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

The authors propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO2/ZrO2/HfO2 (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology.

Frequently asked questions about SRAM IP cores

What is UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT?

UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT is a SRAM IP core from Faraday Technology listed on Semi IP Hub. It is listed with support for umc.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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