Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
SMIC
Category:
SRAM
SMIC 0.13um high density Dual-Port SRAM compiler
0.13um high density Dual-Port SRAM compiler
Overview
0.13um high density Dual-Port SRAM compiler
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 130nm | LL | Silicon Proven |
Specifications
Identity
Part Number
S013HDDP
Vendor
SMIC
Type
Silicon IP
Provider
HQ:
China
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Frequently asked questions about SRAM IP cores
What is SMIC 0.13um high density Dual-Port SRAM compiler?
SMIC 0.13um high density Dual-Port SRAM compiler is a SRAM IP core from SMIC listed on Semi IP Hub. It is listed with support for smic Silicon Proven.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.